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| author | Rob Austein <sra@hactrn.net> | 2020-09-13 23:04:30 +0000 |
|---|---|---|
| committer | Rob Austein <sra@hactrn.net> | 2020-09-13 23:04:30 +0000 |
| commit | b092ffbcbe2c9398494f7dc9db6f0796971633e0 (patch) | |
| tree | 6fabf690f1ebf485a9fea9af5298e44ad2a59a3e /raw-wiki-dump/SunetInitialDevelopment | |
| parent | 9d927e49d9c10fc16c6dfa4a2a96cdb6216e4e2b (diff) | |
Import Cryptech wiki dump
Diffstat (limited to 'raw-wiki-dump/SunetInitialDevelopment')
| -rw-r--r-- | raw-wiki-dump/SunetInitialDevelopment | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/raw-wiki-dump/SunetInitialDevelopment b/raw-wiki-dump/SunetInitialDevelopment new file mode 100644 index 0000000..3626c33 --- /dev/null +++ b/raw-wiki-dump/SunetInitialDevelopment @@ -0,0 +1,86 @@ += Planning for SUNET funded Cryptech Work =
+The following documents the first two development steps in Cryptech
+funded by SUNET. The development is being done by Joachim Strömbergson
+from Secworks AB.
+
+== Step one (Deadline 2014-02-28) ==
+ - Acquire a FPGA development platform.
+DONE. We have a Terasic DE0 board and a Terasic Cyclone V GX starter kit board.
+
+
+ - Create a working development and verification flow from RTL design
+ downto FPGA.
+
+ - Verify the functionality of the SHA-256 core in a physical FPGA.
+
+
+=== Actions for step one ===
+ - Select FPGA development board to acquire
+ - Large enough to test sub systems and possibly a complete HSM.
+ - Good external interfaces for communication with host systems.
+ - Good external interfaces to entropy sources, memories,
+ GPIO. Arduino Shields would be good.
+
+ - Create a survey on interconnect standards usable for Cryptech
+ - Availability and market share/usage in third party cores.
+ - License
+ - Technical details - Bus, fabric, performance etc.
+
+
+ - Create base coretest functionality to allow testing of cores in the
+ FPGA on the development board. Read and write access to registers
+ over a known communication channel.
+
+ - Verify the development flow from Verilog RTL downto FPGA.
+
+ - Verifiera SHA-256 core using coretest.
+
+ - Start FPGA tool survey
+ - What is available as open tools and what is the status.
+ - What is available as open tools from the vendors.
+ - Talk to people in the industry to get their views on an open toolchain.
+
+
+== Step two (Deadline 2014-03-31) ==
+ - Produce first draft of design proposal to the Cryptech True Random Number Generator (TRNG)
+ - Security target, security model and assumptions
+ - Structure, architecture
+ - API
+ - Functionality
+ - Online test system
+ - Verification model
+ - First two entropy sources
+
+ - Complete SHA-1 core. Including functional verification in FPGA.
+
+ - First draft of SHA-256 and SHA-1 core documentation.
+
+
+=== Actions for step two ===
+ - Create template for documentation
+
+ - Collect info on known TRNGs and TRNG strategies
+
+ - Collect info on online tests being used.
+
+ - Create proposal for architecture.
+
+ - Write implementation proposal.
+
+ - Specify API.
+
+ - Write security target and security model.
+
+ - Write assumptions and limitations.
+
+ - Write verification model.
+
+ - Finalize SHA-1 core RTl.
+
+ - Build SHA-1 core in FPGA.
+
+ - Verify SHA-1 functionality in FPGA using coretest.
+
+ - Write documentation for SHA-256 core.
+
+ - Write documentation for SHA-1 core.
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