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| author | Rob Austein <sra@hactrn.net> | 2020-09-13 23:15:43 +0000 |
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| committer | Rob Austein <sra@hactrn.net> | 2020-09-13 23:21:33 +0000 |
| commit | 13d0f55865f8b1b851ce1e84597b144c5fd41662 (patch) | |
| tree | 7b6ff6916f6596f64ec0d2657ae040abd5e18ed9 /raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md | |
| parent | 3aa8b1dd6e0f504ef83da99f8c9cdb2532f948f5 (diff) | |
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| -rw-r--r-- | raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md | 31 |
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diff --git a/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md b/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md deleted file mode 100644 index e512c7d..0000000 --- a/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md +++ /dev/null @@ -1,31 +0,0 @@ -``` -#!htmlcomment - -This page is maintained automatically by a script. Don't modify this page by hand, -your changes will just be overwritten the next time the script runs. Talk to your -Friendly Neighborhood Repository Maintainer if you need to change something here. - -``` - -``` -#!html -<h1>toggle</h1> - -<h2>Introduction</h2> - -<p>This repo contains a simple deign that toggles an ouput pin. The toggle -is in sync with the given sys_clk, but the toggle circuit divides down -the clock. The divisor is build time defined.</p> - -<p>The design is used in the Cryptech FPGA design to observe internal -clock frequencies.</p> - -<h2>Status</h2> - -<p>Has been simulated with Icarus Verilog.</p> -``` - -[[RepositoryIndex(format=table,glob=user/js/toggle)]] - -| Clone `https://git.cryptech.is/user/js/toggle.git` | -|---| |