diff options
author | Rob Austein <sra@hactrn.net> | 2020-09-13 23:06:24 +0000 |
---|---|---|
committer | Rob Austein <sra@hactrn.net> | 2020-09-13 23:06:24 +0000 |
commit | 891730d13b324fad916572a82f0bd610c5de9aad (patch) | |
tree | f46c94ddfff34f15aafe7cac0596716d1c13c412 /raw-wiki-dump/GitRepositories%2Ftest%2Fnovena_base | |
parent | b092ffbcbe2c9398494f7dc9db6f0796971633e0 (diff) |
Rename for conversion
Diffstat (limited to 'raw-wiki-dump/GitRepositories%2Ftest%2Fnovena_base')
-rw-r--r-- | raw-wiki-dump/GitRepositories%2Ftest%2Fnovena_base | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/raw-wiki-dump/GitRepositories%2Ftest%2Fnovena_base b/raw-wiki-dump/GitRepositories%2Ftest%2Fnovena_base deleted file mode 100644 index efd572e..0000000 --- a/raw-wiki-dump/GitRepositories%2Ftest%2Fnovena_base +++ /dev/null @@ -1,47 +0,0 @@ -{{{ -#!htmlcomment - -This page is maintained automatically by a script. Don't modify this page by hand, -your changes will just be overwritten the next time the script runs. Talk to your -Friendly Neighborhood Repository Maintainer if you need to change something here. - -}}} - -{{{ -#!html -<h1>Cryptech Novena FPGA baseline</h1> - -<h2>Introduction</h2> - -<p>This repo contains the Novena FPGA baseline developed as part of the -Cryptech project. The design contains a new FPGA top level, now clock -implementation and reworked EIM interface.</p> - -<p>The main purpose of the baseline is to allow us to run the Cryptech -cores and FPGA system with the general system clock and then interface -to the EIM with the EIM burst clock.</p> - -<h2>Technical details</h2> - -<p>The design tries to be a clean top that is easy for others to work on -and adapt to their needs. The top is stripped from ports not needed for -the baseline. All clock and reset implementation is placed in a separate -module. The EIM interface is in a separate module and then the rest of -the system is in a third module.</p> - -<p>Internally the baseline contains an arbiter to connect cores with a -32-bit memory like interface to the EIM. Finally there is SW to -configure the EIM interface as well as talking to a test core in the -FPGA.</p> - -<p>For information about the EIM clocking and the baseline HW and SW -design, see the documentation.</p> - -<h2>Author</h2> - -<p>The baseline has been written by Pavel Shatov.</p> -}}} - -[[RepositoryIndex(format=table,glob=test/novena_base)]] - -|| Clone `https://git.cryptech.is/test/novena_base.git` || |