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author | Rob Austein <sra@hactrn.net> | 2020-09-13 23:15:43 +0000 |
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committer | Rob Austein <sra@hactrn.net> | 2020-09-13 23:21:33 +0000 |
commit | 13d0f55865f8b1b851ce1e84597b144c5fd41662 (patch) | |
tree | 7b6ff6916f6596f64ec0d2657ae040abd5e18ed9 /raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fecdsalib.md | |
parent | 3aa8b1dd6e0f504ef83da99f8c9cdb2532f948f5 (diff) |
GC
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diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fecdsalib.md b/raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fecdsalib.md deleted file mode 100644 index 2b08cde..0000000 --- a/raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fecdsalib.md +++ /dev/null @@ -1,28 +0,0 @@ -``` -#!htmlcomment - -This page is maintained automatically by a script. Don't modify this page by hand, -your changes will just be overwritten the next time the script runs. Talk to your -Friendly Neighborhood Repository Maintainer if you need to change something here. - -``` - -``` -#!html -<h1>ecdsalib</h1> - -<h2>Core Description</h2> - -<p>This is a library of code common to the ecdsa256 and ecdsa384 cores. See documentation of those cores for details.</p> - -<p>This code was originally repelicated in both of the above cores, but the Xilinx synthesis tools got tetchy about that when trying to build a single image containing both cores.</p> - -<h2>Vendor-specific Primitives</h2> - -<p>Cryptech Alpha platform is based on Xilinx Artix-7 200T FPGA, so this core takes advantage of Xilinx-specific DSP slices to carry out math-intensive operations. All vendor-specific math primitives are placed under /rtl/lowlevel/artix7, the core also offers generic replacements under /rtl/lowlevel/generic, they can be used for simulation with 3rd party tools, that are not aware of Xilinx-specific stuff. Selection of vendor/generic primitives is done in ecdsa_lowlevel_settings.v, when porting to other architectures, only those four low-level modules need to be ported.</p> -``` - -[[RepositoryIndex(format=table,glob=core/math/ecdsalib)]] - -| Clone `https://git.cryptech.is/core/math/ecdsalib.git` | -|---| |