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authorRob Austein <sra@hactrn.net>2020-09-13 23:06:24 +0000
committerRob Austein <sra@hactrn.net>2020-09-13 23:06:24 +0000
commit891730d13b324fad916572a82f0bd610c5de9aad (patch)
treef46c94ddfff34f15aafe7cac0596716d1c13c412 /raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.trac
parentb092ffbcbe2c9398494f7dc9db6f0796971633e0 (diff)
Rename for conversion
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+{{{
+#!htmlcomment
+
+This page is maintained automatically by a script. Don't modify this page by hand,
+your changes will just be overwritten the next time the script runs. Talk to your
+Friendly Neighborhood Repository Maintainer if you need to change something here.
+
+}}}
+
+{{{
+#!html
+<h1>uart</h1>
+
+<p>A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.</p>
+
+<p>This UART used to be in coretest, but has been moved out as a separate
+project.</p>
+
+<p>The current implementation supports the ability to set the bit rate as
+well as number of data- and stop bits by writing to control addresses
+via the control interface.</p>
+}}}
+
+[[RepositoryIndex(format=table,glob=core/comm/uart)]]
+
+|| Clone `https://git.cryptech.is/core/comm/uart.git` ||