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authorRob Austein <sra@hactrn.net>2020-09-13 23:04:30 +0000
committerRob Austein <sra@hactrn.net>2020-09-13 23:04:30 +0000
commitb092ffbcbe2c9398494f7dc9db6f0796971633e0 (patch)
tree6fabf690f1ebf485a9fea9af5298e44ad2a59a3e /raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Feim
parent9d927e49d9c10fc16c6dfa4a2a96cdb6216e4e2b (diff)
Import Cryptech wiki dump
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+{{{
+#!htmlcomment
+
+This page is maintained automatically by a script. Don't modify this page by hand,
+your changes will just be overwritten the next time the script runs. Talk to your
+Friendly Neighborhood Repository Maintainer if you need to change something here.
+
+}}}
+
+{{{
+#!html
+<h1>eim</h1>
+
+<p>Verilog implementation of the eim interface used to connect FPGA cores
+to the Freescale i.MX6 CPU.</p>
+}}}
+
+[[RepositoryIndex(format=table,glob=core/comm/eim)]]
+
+|| Clone `https://git.cryptech.is/core/comm/eim.git` ||