Finally get hanging text in lists mostly right

1 files changed, 3 insertions, 3 deletions

diff --git a/pelican/content/SunetInitialDevelopment.md b/pelican/content/SunetInitialDevelopment.md
index 4ff0580..6fea985 100644
--- a/pelican/content/SunetInitialDevelopment.md
+++ b/pelican/content/SunetInitialDevelopment.md
@@ -16,10 +16,10 @@ DONE. We have a Terasic DE0 board and a Terasic Cyclone V GX starter kit board.
 
 
     - Create a working development and verification flow from RTL design
-
    downto FPGA.
 
 
+
     - Verify the functionality of the SHA-256 core in a physical FPGA.
 
 
@@ -30,10 +30,10 @@ DONE. We have a Terasic DE0 board and a Terasic Cyclone V GX starter kit board.
         - Large enough to test sub systems and possibly a complete HSM.
         - Good external interfaces for communication with host systems.
         - Good external interfaces to entropy sources, memories,
-
      GPIO. Arduino Shields would be good.
 
 
+
     - Create a survey on interconnect standards usable for Cryptech
         - Availability and market share/usage in third party cores.
         - License
@@ -43,11 +43,11 @@ DONE. We have a Terasic DE0 board and a Terasic Cyclone V GX starter kit board.
 
 
     - Create base coretest functionality to allow testing of cores in the
-
      FPGA on the development board. Read and write access to registers
      over a known communication channel.
 
 
+
     - Verify the development flow from Verilog RTL downto FPGA.