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| author | Rob Austein <sra@hactrn.net> | 2021-02-15 07:18:12 +0000 |
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| committer | Rob Austein <sra@hactrn.net> | 2021-02-15 07:18:12 +0000 |
| commit | dd255ef58a617214ea3ece613c417af1fc1549ec (patch) | |
| tree | 2c427130fd2c90f92d478535e64a125c38cb5fef /pelican/content/EDAToolchainSurvey.md | |
| parent | 3bfd6f7d2c45b44ae3ef0616f40368d59eae0c68 (diff) | |
Authors
Diffstat (limited to 'pelican/content/EDAToolchainSurvey.md')
| -rw-r--r-- | pelican/content/EDAToolchainSurvey.md | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/pelican/content/EDAToolchainSurvey.md b/pelican/content/EDAToolchainSurvey.md index cdb1e4d..b8632a6 100644 --- a/pelican/content/EDAToolchainSurvey.md +++ b/pelican/content/EDAToolchainSurvey.md @@ -1,4 +1,5 @@ Title: EDAToolchainSurvey +Author: trac Date: 2016-12-15 22:43 The major issue is finding tools that allows a designer, user to verify that the RTL source code (in Verilog or VHDL) matches what is generated at the physical level. As part of the project we need to investigate the current status of open tools in the toolchain for implementation and verification of hardware. This includes RTL simulation, synthesis, place & route, netlist verification, timing analysis and configuration file generation and analysis. (This implies that the target is an FPGA.). If there are no open tools we need to find ways of verifying pre- and post-functionality to check that the black box tool does not alter (subvert) the design in ways not intended. |