Images

12 files changed, 25 insertions, 25 deletions

diff --git a/markdown/AlphaBoardPictures.md b/markdown/AlphaBoardPictures.md
index 08c7d68..27caebe 100644
--- a/markdown/AlphaBoardPictures.md
+++ b/markdown/AlphaBoardPictures.md
@@ -8,5 +8,5 @@ The current revision of the Alpha board is rev03.
 rev01 was the board known as the 'dev-bridge'.
 rev02 was functionally the same as the rev03, but in another form factor.
 
-[[Image(Alpha_rev03_top_med.jpg)]]
-[[Image(Alpha_rev03_bottom_med.jpg)]]
+<img src="Alpha_rev03_top_med.jpg">
+<img src="Alpha_rev03_bottom_med.jpg">
diff --git a/markdown/AlphaSealedBags.md b/markdown/AlphaSealedBags.md
index e99dbca..0f4d720 100644
--- a/markdown/AlphaSealedBags.md
+++ b/markdown/AlphaSealedBags.md
@@ -15,7 +15,7 @@ At this time, we do not keep records of which exact unit was sent to whom.
 
 This is a picture of the currently used bags:
 
-[[Image(Alpha_tamper_bag_2016-12-16.png, 640px)]]
+<img src="Alpha_tamper_bag_2016-12-16.png">
 
 
 
diff --git a/markdown/CoretestHashesC5G.md b/markdown/CoretestHashesC5G.md
index 7cc2e30..6d98aea 100644
--- a/markdown/CoretestHashesC5G.md
+++ b/markdown/CoretestHashesC5G.md
@@ -19,7 +19,7 @@ The test setup consists of:
 - The TerasIC Cyclone 5 GX Starter Kit (C5G) board.
 
 
-[[Image(http://www.terasic.com.tw/attachment/archive/830/image/image_74_thumb.jpg)]]
+<img src="http://www.terasic.com.tw/attachment/archive/830/image/image_74_thumb.jpg">
 
 *The TerasIC Cyclone 5 GX Starter Kit board.*
 
@@ -57,7 +57,7 @@ interface connected to a FPGA device. The subsystem consists of:
 
   well as connecting the rxd and txd ports on the uart to external pins as well as clk and reset. This core repo also contains the Python command line program hash_tester we will be using to talk to coretester and perform tests of the sha1 and sha256 cores.
 
-[[Image(coretest_hashes.png)]]
+<img src="coretest_hashes.png">
 
 *The coretest_hashes subsystem with sha1 and sha256 cores. The system is connected to a host computer via a serial interface.*
 
diff --git a/markdown/CoretestHashesNovena.md b/markdown/CoretestHashesNovena.md
index 6bc9c2a..3dfc8cd 100644
--- a/markdown/CoretestHashesNovena.md
+++ b/markdown/CoretestHashesNovena.md
@@ -7,7 +7,7 @@ Cryptech subsystem on a Novena PVT1 development board.
 
 [Novena](http://www.kosagi.com/w/index.php?title=Novena_Main_Page) is an open hardware and F/OSS-friendly computing platform.
 
-[[Image(http://bunniefoo.com/novena/pvt1_release/novena_pvt1e_top_sm.jpg)]]
+<img src="http://bunniefoo.com/novena/pvt1_release/novena_pvt1e_top_sm.jpg">
 
 It is a small single-board Linux PC, which happens to include a Xilinx [Spartan-6 FPGA]. This, together with the TerasIC [http://trac.cryptech.is/wiki/CoretestHashesC5G Cyclone 5 GX](http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/lx.html), is what we are using to develop and test the Cryptech cores.
 
diff --git a/markdown/DevBridgeBoard.md b/markdown/DevBridgeBoard.md
index f4dde47..41a12c4 100644
--- a/markdown/DevBridgeBoard.md
+++ b/markdown/DevBridgeBoard.md
@@ -11,13 +11,13 @@ Schematics and layouts are at [user/ft/stm32-dev-bridge/hardware/rev01](https://
 
 High resolution pictures of rev01 of the dev-bridge board are attached at the bottom of this page, but the following should be more than sufficient to read the silkscreens.
 
-[[Image(dev-bridge_rev01_front_medium.jpg​)]]
+<img src="dev-bridge_rev01_front_medium.jpg​">
 
-[[Image(dev-bridge_rev01_back_medium.jpg​)]]
+<img src="dev-bridge_rev01_back_medium.jpg​">
 
 Here is the board mounted on the Novena, attached to the programmer:
 
-[[Image(IMG_9983s.jpg)]]
+<img src="IMG_9983s.jpg">
 
 Note that it's rather bigger than the Netgear enclosure I use to transport the Novena. (Not only does it protect the board, but I have this superstition that TSA is more comfortable with a home gateway than a bare motherboard.)
 
diff --git a/markdown/GettingStartedNovena.md b/markdown/GettingStartedNovena.md
index 66f220c..97668a1 100644
--- a/markdown/GettingStartedNovena.md
+++ b/markdown/GettingStartedNovena.md
@@ -4,7 +4,7 @@
 
 ## The Novena Board
 
-[[Image(http://bunniefoo.com/novena/pvt1_release/novena_pvt1e_top_sm.jpg)]]
+<img src="http://bunniefoo.com/novena/pvt1_release/novena_pvt1e_top_sm.jpg">
 
 [Novena](http://www.kosagi.com/w/index.php?title=Novena_Main_Page) is an open hardware and F/OSS-friendly computing platform. It is a small single-board Linux PC, with a Freescale i.MX6 (ARM
 Cortex-A9) CPU and a Xilinx Spartan-6 LX45 FPGA.
@@ -26,7 +26,7 @@ $ sudo apt-get upgrade
 
 ## The Avalanche Noise Board
 
-[[Image(rev03-on-novena.jpg, 40%)]]
+<img src="rev03-on-novena.jpg">
 
 The avalanche noise board is a Novena daughter board that contains a zener-diode noise circuit that can be read directly by the FPGA.
 
diff --git a/markdown/Hardware.md b/markdown/Hardware.md
index e271794..eaba3fa 100644
--- a/markdown/Hardware.md
+++ b/markdown/Hardware.md
@@ -12,7 +12,7 @@ Various generic FPGA development boards.
 
 An Alpha version of a CrypTech HSM, currently in early design
 
-[[Image(cryptech-g3.png)]]
+<img src="cryptech-g3.png">
 
 There is no real tamper wrapping and no tamper sensors.  The tamper switch is used to simulate tamper detection to test the system's tamper reaction(s).
 
diff --git a/markdown/NoisyDiode.md b/markdown/NoisyDiode.md
index 6a9caee..b4afe5a 100644
--- a/markdown/NoisyDiode.md
+++ b/markdown/NoisyDiode.md
@@ -7,21 +7,21 @@ Avalanche breakdown is a physical process that occurs when current is forced bac
 
 The unamplified noise looks like this:
 
-[[Image(noise1.jpg)]]
+<img src="noise1.jpg">
 
 After amplification, details are lost but the signal is now 3.3V (blue is noise before amplification, yellow is amplified)
 
-[[Image(noise2.jpg)]]
+<img src="noise2.jpg">
 
 Many implementations on the Internet feed a similar signal into an ADC (Analog Digital converter) and use the resulting data value at the time of the sampling as entropy. The Cryptech project believes a more robust way of extracting entropy is to instead feed the noise to a Schmitt trigger and then measure the time between rising edges. This would be more robust since any analog reading of the noise (such as with an ADC) will be sensitive to changes in temperature, supplied voltage and component aging.
 
 After beeing fed through a Schmitt trigger, the noise looks like this (yellow signal, blue is just a 4 MHz clock):
 
-[[Image(noise-schmitt.jpg)]]
+<img src="noise-schmitt.jpg">
 
 The Cryptech project has to date made a couple of different hardware entropy source boards, but they all share the same design for the avalanche noise source. The core parts of the circuit are shown below. Git repository with full schematics and source code is linked at the bottom of this page.
 
-[[Image(noise-schematics.png)]]
+<img src="noise-schematics.png">
 
 Links:
 
diff --git a/markdown/OpenCryptoChip.md b/markdown/OpenCryptoChip.md
index 521d19c..145ae07 100644
--- a/markdown/OpenCryptoChip.md
+++ b/markdown/OpenCryptoChip.md
@@ -4,7 +4,7 @@
 
 ## The Layer Cake Architecture Picture
 \\
-[[Image(layer-cake.jpg)]]
+<img src="layer-cake.jpg">
 
 \\
 \\
@@ -23,7 +23,7 @@
 * Password management
 
 
-[[Image(cryptech venn.png)]]
+<img src="cryptech venn.png">
 
 ## Basic Functions of Crypto Chip
 
diff --git a/markdown/RoughV1.md b/markdown/RoughV1.md
index 1891975..95476aa 100644
--- a/markdown/RoughV1.md
+++ b/markdown/RoughV1.md
@@ -19,11 +19,11 @@ source out of the can.  for v.2 (or whatever) we would move it down to the FPGA
 Verilog.
 
 ## FPGA Overview
-[[Image(HW_sketch_v0001.png)]]
+<img src="HW_sketch_v0001.png">
 \\
 \\
 ## Sketch of TRNG Chain
-[[Image(HW_RNG.png​)]]
+<img src="HW_RNG.png​">
 \\
 \\
 
diff --git a/markdown/StateOfPlay.md b/markdown/StateOfPlay.md
index b9b448b..06ad190 100644
--- a/markdown/StateOfPlay.md
+++ b/markdown/StateOfPlay.md
@@ -80,22 +80,22 @@ See [Libraries Guide for HDL Designs]]([http://www.xilinx.com/support/documentat
 
 ### Module relationships in core/novena build
 
-[[Image(novena__linkcells.svg)]]
+<img src="novena__linkcells.svg">
 
 ### Module relationships in core/novena_i2c_simple build
 
-[[Image(novena_i2c_simple__linkcells.svg)]]
+<img src="novena_i2c_simple__linkcells.svg">
 
 ### Module relationships in core/novena_eim build
 
-[[Image(novena_eim__linkcells.svg)]]
+<img src="novena_eim__linkcells.svg">
 
 ### Module relationships in cores/trng build
 
 By special request, here's a graph for the TRNG too, even though we
 don't yet have a way to speak to it from the Novena:
 
-[[Image(trng__linkcells.svg)]]
+<img src="trng__linkcells.svg">
 
 ## C Code
 
diff --git a/markdown/UsingSTLink.md b/markdown/UsingSTLink.md
index 02cc21e..18c0807 100644
--- a/markdown/UsingSTLink.md
+++ b/markdown/UsingSTLink.md
@@ -23,7 +23,7 @@ on the Alpha board (top, just left of center).
 This photo shows the correct orientation of the cables (both boards
 oriented so that the logo is right-side up):
 
-[[Image(IMG_20170512_205557_s.jpg)]]
+<img src="IMG_20170512_205557_s.jpg">
 
 NOTE: The STM boards have an unfortunate tendency to short unexpectedly, so
 I recommend putting them in an enclosure. In this case, I've cut holes in