Add image links

Clean up whacky invisible unicode characters in links on a couple of source packages

16 files changed, 38 insertions, 34 deletions

diff --git a/.gitignore b/.gitignore
index 3d9d661..423a040 100644
--- a/.gitignore
+++ b/.gitignore
@@ -3,6 +3,6 @@
 TAGS
 __pycache__
 attachments
-trac.db
+pelican/content/*/*
 pelican/pelicanconf.py
-pelican/images
+trac.db
diff --git a/extract.py b/extract.py
index ffd183b..9466769 100755
--- a/extract.py
+++ b/extract.py
@@ -50,7 +50,7 @@ def attachment_link(row):
     fn2 = os.path.splitext(row["filename"])[1]
     return \
         os.path.join("attachments", "wiki", h1[:3], h1, h2 + fn2), \
-        os.path.join("pelican", "images", urllib.parse.quote(row.id, ""), urllib.parse.quote(row.filename, ""))
+        os.path.join("pelican", "content", urllib.parse.quote(row.id, ""), urllib.parse.quote(row.filename, ""))
 
 class Filter:
 
@@ -76,7 +76,7 @@ def main():
     for dn in ("wiki", "pelican"):
         shutil.rmtree(dn)
 
-    for dn in ("wiki", "pelican/content/images", "pelican/content/pages"):
+    for dn in ("wiki", "pelican/content"):
         os.makedirs(dn)
 
     os.link("pelicanconf.py", "pelican/pelicanconf.py")
@@ -92,7 +92,7 @@ def main():
             print(slug, row.version)
             with open("wiki/{}.trac".format(slug), "w") as f:
                 f.write(row.text)
-            md = trac2md.WikiToMD(row.text)
+            md = trac2md.WikiToMD(row.text, slug)
             with open("pelican/content/{}.md".format(slug), "w") as f:
                 f.write(md)
 
diff --git a/pelican/content/AlphaBoardPictures.md b/pelican/content/AlphaBoardPictures.md
index 27caebe..9e006f0 100644
--- a/pelican/content/AlphaBoardPictures.md
+++ b/pelican/content/AlphaBoardPictures.md
@@ -8,5 +8,5 @@ The current revision of the Alpha board is rev03.
 rev01 was the board known as the 'dev-bridge'.
 rev02 was functionally the same as the rev03, but in another form factor.
 
-<img src="Alpha_rev03_top_med.jpg">
-<img src="Alpha_rev03_bottom_med.jpg">
+![Alpha_rev03_top_med.jpg]({attach}AlphaBoardPictures/Alpha_rev03_top_med.jpg)
+![Alpha_rev03_bottom_med.jpg]({attach}AlphaBoardPictures/Alpha_rev03_bottom_med.jpg)
diff --git a/pelican/content/AlphaSealedBags.md b/pelican/content/AlphaSealedBags.md
index 0f4d720..a69a66c 100644
--- a/pelican/content/AlphaSealedBags.md
+++ b/pelican/content/AlphaSealedBags.md
@@ -15,7 +15,7 @@ At this time, we do not keep records of which exact unit was sent to whom.
 
 This is a picture of the currently used bags:
 
-<img src="Alpha_tamper_bag_2016-12-16.png">
+![Alpha_tamper_bag_2016-12-16.png]({attach}AlphaSealedBags/Alpha_tamper_bag_2016-12-16.png)
 
 
 
diff --git a/pelican/content/CoretestHashesC5G.md b/pelican/content/CoretestHashesC5G.md
index 6d98aea..20a3faa 100644
--- a/pelican/content/CoretestHashesC5G.md
+++ b/pelican/content/CoretestHashesC5G.md
@@ -57,7 +57,7 @@ interface connected to a FPGA device. The subsystem consists of:
 
   well as connecting the rxd and txd ports on the uart to external pins as well as clk and reset. This core repo also contains the Python command line program hash_tester we will be using to talk to coretester and perform tests of the sha1 and sha256 cores.
 
-<img src="coretest_hashes.png">
+![coretest_hashes.png]({attach}CoretestHashesC5G/coretest_hashes.png)
 
 *The coretest_hashes subsystem with sha1 and sha256 cores. The system is connected to a host computer via a serial interface.*
 
diff --git a/pelican/content/DevBridgeBoard.md b/pelican/content/DevBridgeBoard.md
index 41a12c4..2df3ac4 100644
--- a/pelican/content/DevBridgeBoard.md
+++ b/pelican/content/DevBridgeBoard.md
@@ -11,13 +11,13 @@ Schematics and layouts are at [user/ft/stm32-dev-bridge/hardware/rev01](https://
 
 High resolution pictures of rev01 of the dev-bridge board are attached at the bottom of this page, but the following should be more than sufficient to read the silkscreens.
 
-<img src="dev-bridge_rev01_front_medium.jpg​">
+![dev-bridge_rev01_front_medium.jpg]({attach}DevBridgeBoard/dev-bridge_rev01_front_medium.jpg)
 
-<img src="dev-bridge_rev01_back_medium.jpg​">
+![dev-bridge_rev01_back_medium.jpg]({attach}DevBridgeBoard/dev-bridge_rev01_back_medium.jpg)
 
 Here is the board mounted on the Novena, attached to the programmer:
 
-<img src="IMG_9983s.jpg">
+![IMG_9983s.jpg]({attach}DevBridgeBoard/IMG_9983s.jpg)
 
 Note that it's rather bigger than the Netgear enclosure I use to transport the Novena. (Not only does it protect the board, but I have this superstition that TSA is more comfortable with a home gateway than a bare motherboard.)
 
diff --git a/pelican/content/GettingStartedNovena.md b/pelican/content/GettingStartedNovena.md
index 97668a1..8c58aed 100644
--- a/pelican/content/GettingStartedNovena.md
+++ b/pelican/content/GettingStartedNovena.md
@@ -26,7 +26,7 @@ $ sudo apt-get upgrade
 
 ## The Avalanche Noise Board
 
-<img src="rev03-on-novena.jpg">
+![rev03-on-novena.jpg]({attach}GettingStartedNovena/rev03-on-novena.jpg)
 
 The avalanche noise board is a Novena daughter board that contains a zener-diode noise circuit that can be read directly by the FPGA.
 
diff --git a/pelican/content/Hardware.md b/pelican/content/Hardware.md
index eaba3fa..fbdac48 100644
--- a/pelican/content/Hardware.md
+++ b/pelican/content/Hardware.md
@@ -12,7 +12,7 @@ Various generic FPGA development boards.
 
 An Alpha version of a CrypTech HSM, currently in early design
 
-<img src="cryptech-g3.png">
+![cryptech-g3.png]({attach}Hardware/cryptech-g3.png)
 
 There is no real tamper wrapping and no tamper sensors.  The tamper switch is used to simulate tamper detection to test the system's tamper reaction(s).
 
diff --git a/pelican/content/NoisyDiode.md b/pelican/content/NoisyDiode.md
index b4afe5a..46e5ec2 100644
--- a/pelican/content/NoisyDiode.md
+++ b/pelican/content/NoisyDiode.md
@@ -7,21 +7,21 @@ Avalanche breakdown is a physical process that occurs when current is forced bac
 
 The unamplified noise looks like this:
 
-<img src="noise1.jpg">
+![noise1.jpg]({attach}NoisyDiode/noise1.jpg)
 
 After amplification, details are lost but the signal is now 3.3V (blue is noise before amplification, yellow is amplified)
 
-<img src="noise2.jpg">
+![noise2.jpg]({attach}NoisyDiode/noise2.jpg)
 
 Many implementations on the Internet feed a similar signal into an ADC (Analog Digital converter) and use the resulting data value at the time of the sampling as entropy. The Cryptech project believes a more robust way of extracting entropy is to instead feed the noise to a Schmitt trigger and then measure the time between rising edges. This would be more robust since any analog reading of the noise (such as with an ADC) will be sensitive to changes in temperature, supplied voltage and component aging.
 
 After beeing fed through a Schmitt trigger, the noise looks like this (yellow signal, blue is just a 4 MHz clock):
 
-<img src="noise-schmitt.jpg">
+![noise-schmitt.jpg]({attach}NoisyDiode/noise-schmitt.jpg)
 
 The Cryptech project has to date made a couple of different hardware entropy source boards, but they all share the same design for the avalanche noise source. The core parts of the circuit are shown below. Git repository with full schematics and source code is linked at the bottom of this page.
 
-<img src="noise-schematics.png">
+![noise-schematics.png]({attach}NoisyDiode/noise-schematics.png)
 
 Links:
 
diff --git a/pelican/content/OpenCryptoChip.md b/pelican/content/OpenCryptoChip.md
index ab250a3..c8163f8 100644
--- a/pelican/content/OpenCryptoChip.md
+++ b/pelican/content/OpenCryptoChip.md
@@ -5,7 +5,7 @@
 ## The Layer Cake Architecture Picture
   
 
-<img src="layer-cake.jpg">
+![layer-cake.jpg]({attach}OpenCryptoChip/layer-cake.jpg)
 
   
 
@@ -26,7 +26,7 @@
 * Password management
 
 
-<img src="cryptech venn.png">
+![cryptech venn.png]({attach}OpenCryptoChip/cryptech%20venn.png)
 
 ## Basic Functions of Crypto Chip
 
diff --git a/pelican/content/RoughV1.md b/pelican/content/RoughV1.md
index 1c0ec56..ada39d9 100644
--- a/pelican/content/RoughV1.md
+++ b/pelican/content/RoughV1.md
@@ -19,13 +19,13 @@ source out of the can.  for v.2 (or whatever) we would move it down to the FPGA
 Verilog.
 
 ## FPGA Overview
-<img src="HW_sketch_v0001.png">
+![HW_sketch_v0001.png]({attach}RoughV1/HW_sketch_v0001.png)
   
 
   
 
 ## Sketch of TRNG Chain
-<img src="HW_RNG.png​">
+![HW_RNG.png]({attach}RoughV1/HW_RNG.png)
   
 
   
diff --git a/pelican/content/StateOfPlay.md b/pelican/content/StateOfPlay.md
index 06ad190..524971b 100644
--- a/pelican/content/StateOfPlay.md
+++ b/pelican/content/StateOfPlay.md
@@ -80,22 +80,22 @@ See [Libraries Guide for HDL Designs]]([http://www.xilinx.com/support/documentat
 
 ### Module relationships in core/novena build
 
-<img src="novena__linkcells.svg">
+![novena__linkcells.svg]({attach}StateOfPlay/novena__linkcells.svg)
 
 ### Module relationships in core/novena_i2c_simple build
 
-<img src="novena_i2c_simple__linkcells.svg">
+![novena_i2c_simple__linkcells.svg]({attach}StateOfPlay/novena_i2c_simple__linkcells.svg)
 
 ### Module relationships in core/novena_eim build
 
-<img src="novena_eim__linkcells.svg">
+![novena_eim__linkcells.svg]({attach}StateOfPlay/novena_eim__linkcells.svg)
 
 ### Module relationships in cores/trng build
 
 By special request, here's a graph for the TRNG too, even though we
 don't yet have a way to speak to it from the Novena:
 
-<img src="trng__linkcells.svg">
+![trng__linkcells.svg]({attach}StateOfPlay/trng__linkcells.svg)
 
 ## C Code
 
diff --git a/pelican/content/UsingSTLink.md b/pelican/content/UsingSTLink.md
index 18c0807..1c6f7da 100644
--- a/pelican/content/UsingSTLink.md
+++ b/pelican/content/UsingSTLink.md
@@ -23,7 +23,7 @@ on the Alpha board (top, just left of center).
 This photo shows the correct orientation of the cables (both boards
 oriented so that the logo is right-side up):
 
-<img src="IMG_20170512_205557_s.jpg">
+![IMG_20170512_205557_s.jpg]({attach}UsingSTLink/IMG_20170512_205557_s.jpg)
 
 NOTE: The STM boards have an unfortunate tendency to short unexpectedly, so
 I recommend putting them in an enclosure. In this case, I've cut holes in
diff --git a/trac2md.py b/trac2md.py
index c022899..ee9d80a 100755
--- a/trac2md.py
+++ b/trac2md.py
@@ -12,6 +12,7 @@ import shutil
 import os
 from base64 import b64decode
 from datetime import datetime
+from urllib.parse import quote
 
 wikilink_pattern = re.compile('\[http(.*)\]')
 wikilink_extract = re.compile('\[(.*)\]')
@@ -105,13 +106,16 @@ def convert_strike(line):
             pass
     return line
 
-def convert_image(line):
+def convert_image(line, slug):
     image_result = image_pattern.search(line)
     if image_result:
         try:
             image_text = image_result.group(1).split(",")[0].strip()
             old_text = image_result.group(0)
-            new_text = "<img src=\"{}\">".format(image_text)
+            if "://" in image_text:
+                new_text = "<img src=\"{}\">".format(image_text)
+            else:
+                new_text = "![{}]({{attach}}{}/{})".format(image_text, slug, quote(image_text, ""))
             line = line.replace(old_text, new_text)
         except:
             pass
@@ -123,7 +127,7 @@ def convert_linebreak(line):
         line = line[:-2] + "  "
     return line
 
-def WikiToMD(content):
+def WikiToMD(content, slug):
     ''' Convert wiki/RST format to Markdown.  Code blocks, bold/italics,
     wiki links, lists, striked text, and headers. '''
 
@@ -219,7 +223,7 @@ def WikiToMD(content):
             line = convert_strike(line)
 
             # Convert images
-            line = convert_image(line)
+            line = convert_image(line, slug)
 
             # Convert line breaks
             line = convert_linebreak(line)
diff --git a/wiki/DevBridgeBoard.trac b/wiki/DevBridgeBoard.trac
index e601fda..e2c6c1c 100644
--- a/wiki/DevBridgeBoard.trac
+++ b/wiki/DevBridgeBoard.trac
@@ -11,9 +11,9 @@ Schematics and layouts are at [https://wiki.cryptech.is/browser/user/ft/stm32-de
 

 High resolution pictures of rev01 of the dev-bridge board are attached at the bottom of this page, but the following should be more than sufficient to read the silkscreens.

 

-[[Image(dev-bridge_rev01_front_medium.jpg​)]]

+[[Image(dev-bridge_rev01_front_medium.jpg)]]

 

-[[Image(dev-bridge_rev01_back_medium.jpg​)]]

+[[Image(dev-bridge_rev01_back_medium.jpg)]]

 

 Here is the board mounted on the Novena, attached to the programmer:

 

diff --git a/wiki/RoughV1.trac b/wiki/RoughV1.trac
index a142056..57dfda9 100644
--- a/wiki/RoughV1.trac
+++ b/wiki/RoughV1.trac
@@ -23,7 +23,7 @@ Verilog.
 \\

 \\

 == Sketch of TRNG Chain ==

-[[Image(HW_RNG.png​)]]

+[[Image(HW_RNG.png)]]

 \\

 \\