blob: 837f633d63c27d8719b990b24cc898d039825f96 (
plain) (
tree)
|
|
{{{
#!htmlcomment
This page is maintained automatically by a script. Don't modify this page by hand,
your changes will just be overwritten the next time the script runs. Talk to your
Friendly Neighborhood Repository Maintainer if you need to change something here.
}}}
{{{
#!html
<h1>core/lib</h1>
<p>This repository contains common modules instantiated by other cores:</p>
<ul>
<li><p><strong>lowlevel</strong> contains modules for math operations (addition, subtraction, etc). Two sets of modules are provided: <strong>generic</strong> ones can be used during simulation and when porting to a different architecture, modules from <strong>artix7</strong> should be used when building a bitstream for the Alpha board. To use the modules first <code>`include "cryptech_primitive_switch.vh"</code>, then instantiate them using <code>`CRYPTECH_PRIMITIVE_*</code> macro.</p></li>
<li><p><strong>memory</strong> contains wrappers for block memories:</p>
<ul>
<li><code>bram_1rw_readfirst</code> is single read-write port</li>
<li><code>bram_1rw_1ro_readfirst</code> is one read-write, one read-only port</li>
<li><code>bram_1wo_1ro_readfirst</code> is one write-only, one read-only port (useful for storing private keys)</li>
</ul></li>
<li><p><strong>modular</strong> contains multiprecision modular adder and subtractor</p></li>
<li><p><strong>multiword</strong> contains multiprecision integer comparator and mover/copier</p></li>
<li><p><strong>util</strong> has the following:</p>
<ul>
<li><code>cryptech_clog2.vh</code> replacement for Xilinx' notorious clog2()</li>
</ul></li>
</ul>
}}}
[[RepositoryIndex(format=table,glob=core/lib)]]
|| Clone `https://git.cryptech.is/core/lib.git` ||
|
