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<h1>uart</h1>
<p>A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.</p>
<p>This UART used to be in coretest, but has been moved out as a separate
project.</p>
<p>The current implementation supports the ability to set the bit rate as
well as number of data- and stop bits by writing to control addresses
via the control interface.</p>
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[[RepositoryIndex(format=table,glob=core/comm/uart)]]
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