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module modexpng_storage_block
(
clk, rst,
wr_wide_xy_ena,
wr_wide_xy_bank,
wr_wide_xy_addr,
wr_wide_x_din,
wr_wide_y_din,
wr_narrow_xy_ena,
wr_narrow_xy_bank,
wr_narrow_xy_addr,
wr_narrow_x_din,
wr_narrow_y_din,
rd_wide_xy_ena,
rd_wide_xy_ena_aux,
rd_wide_xy_bank,
rd_wide_xy_bank_aux,
rd_wide_xy_addr,
rd_wide_xy_addr_aux,
rd_wide_x_dout,
rd_wide_y_dout,
rd_wide_x_dout_aux,
rd_wide_y_dout_aux,
rd_narrow_xy_ena,
rd_narrow_xy_bank,
rd_narrow_xy_addr,
rd_narrow_x_dout,
rd_narrow_y_dout
);
//
// Headers
//
`include "../rtl_1/modexpng_parameters_x8_old.vh"
//
// Ports
//
input clk;
input rst;
input wr_wide_xy_ena;
input [ 1:0] wr_wide_xy_bank;
input [ 7:0] wr_wide_xy_addr;
input [17:0] wr_wide_x_din;
input [17:0] wr_wide_y_din;
input wr_narrow_xy_ena;
input [ 1:0] wr_narrow_xy_bank;
input [ 7:0] wr_narrow_xy_addr;
input [17:0] wr_narrow_x_din;
input [17:0] wr_narrow_y_din;
input rd_wide_xy_ena;
input rd_wide_xy_ena_aux;
input [ 1:0] rd_wide_xy_bank;
input [ 1:0] rd_wide_xy_bank_aux;
input [ 8*NUM_MULTS/2-1:0] rd_wide_xy_addr;
input [ 8-1:0] rd_wide_xy_addr_aux;
output [18*NUM_MULTS/2-1:0] rd_wide_x_dout;
output [18*NUM_MULTS/2-1:0] rd_wide_y_dout;
output [ 18-1:0] rd_wide_x_dout_aux;
output [ 18-1:0] rd_wide_y_dout_aux;
input rd_narrow_xy_ena;
input [ 1:0] rd_narrow_xy_bank;
input [ 7:0] rd_narrow_xy_addr;
output [18-1:0] rd_narrow_x_dout;
output [18-1:0] rd_narrow_y_dout;
//
// Internal Registers
//
reg rd_wide_xy_reg_ena = 1'b0;
reg rd_wide_xy_reg_ena_aux = 1'b0;
reg rd_narrow_xy_reg_ena = 1'b0;
always @(posedge clk) begin
//
rd_wide_xy_reg_ena <= rst ? 1'b0 : rd_wide_xy_ena;
rd_wide_xy_reg_ena_aux <= rst ? 1'b0 : rd_wide_xy_ena_aux;
rd_narrow_xy_reg_ena <= rst ? 1'b0 : rd_narrow_xy_ena;
//
end
//
// Helper Signals
//
wire [2+8-1:0] wr_wide_xy_offset;
wire [2+8-1:0] rd_wide_xy_offset[0:NUM_MULTS/2-1];
wire [2+8-1:0] rd_wide_xy_offset_aux;
wire [2+8-1:0] wr_narrow_xy_offset;
wire [2+8-1:0] rd_narrow_xy_offset;
assign wr_wide_xy_offset = {wr_wide_xy_bank, wr_wide_xy_addr};
assign rd_wide_xy_offset_aux = {rd_wide_xy_bank_aux, rd_wide_xy_addr_aux};
assign wr_narrow_xy_offset = {wr_narrow_xy_bank, wr_narrow_xy_addr};
assign rd_narrow_xy_offset = {rd_narrow_xy_bank, rd_narrow_xy_addr};
//
// "Wide" Storage
//
genvar z;
generate for (z=0; z<(NUM_MULTS/2); z=z+1)
begin : gen_wide_bram
//
assign rd_wide_xy_offset[z] = {rd_wide_xy_bank, rd_wide_xy_addr[8*z+:8]};
//
ip_bram_18k wide_bram_x
(
.clka (clk),
.clkb (clk),
.ena (wr_wide_xy_ena),
.wea (wr_wide_xy_ena),
.addra (wr_wide_xy_offset),
.dina (wr_wide_x_din),
.enb (rd_wide_xy_ena),
.regceb (rd_wide_xy_reg_ena),
.addrb (rd_wide_xy_offset[z]),
.doutb (rd_wide_x_dout[18*z+:18])
);
//
ip_bram_18k wide_bram_y
(
.clka (clk),
.clkb (clk),
.ena (wr_wide_xy_ena),
.wea (wr_wide_xy_ena),
.addra (wr_wide_xy_offset),
.dina (wr_wide_y_din),
.enb (rd_wide_xy_ena),
.regceb (rd_wide_xy_reg_ena),
.addrb (rd_wide_xy_offset[z]),
.doutb (rd_wide_y_dout[18*z+:18])
);
//
end
endgenerate
//
// Auxilary Storage
//
ip_bram_18k wide_bram_x_aux
(
.clka (clk),
.clkb (clk),
.ena (wr_wide_xy_ena),
.wea (wr_wide_xy_ena),
.addra (wr_wide_xy_offset),
.dina (wr_wide_x_din),
.enb (rd_wide_xy_ena_aux),
.regceb (rd_wide_xy_reg_ena_aux),
.addrb (rd_wide_xy_offset_aux),
.doutb (rd_wide_x_dout_aux)
);
//
ip_bram_18k wide_bram_y_aux
(
.clka (clk),
.clkb (clk),
.ena (wr_wide_xy_ena),
.wea (wr_wide_xy_ena),
.addra (wr_wide_xy_offset),
.dina (wr_wide_y_din),
.enb (rd_wide_xy_ena_aux),
.regceb (rd_wide_xy_reg_ena_aux),
.addrb (rd_wide_xy_offset_aux),
.doutb (rd_wide_y_dout_aux)
);
//
// "Narrow" Storage
//
ip_bram_18k narrow_bram_x
(
.clka (clk),
.clkb (clk),
.ena (wr_narrow_xy_ena),
.wea (wr_narrow_xy_ena),
.addra (wr_narrow_xy_offset),
.dina (wr_narrow_x_din),
.enb (rd_narrow_xy_ena),
.regceb (rd_narrow_xy_reg_ena),
.addrb (rd_narrow_xy_offset),
.doutb (rd_narrow_x_dout)
);
ip_bram_18k narrow_bram_y
(
.clka (clk),
.clkb (clk),
.ena (wr_narrow_xy_ena),
.wea (wr_narrow_xy_ena),
.addra (wr_narrow_xy_offset),
.dina (wr_narrow_y_din),
.enb (rd_narrow_xy_ena),
.regceb (rd_narrow_xy_reg_ena),
.addrb (rd_narrow_xy_offset),
.doutb (rd_narrow_y_dout)
);
endmodule
|
