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//======================================================================
//
// Copyright (c) 2019, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
//   be used to endorse or promote products derived from this software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================

module modexpng_sdp_36k_x32_x16_wrapper_generic
(
    clk, clk_bus,
    
    ena, wea,
    addra, dina,
    
    enb,
    addrb, doutb
);


    //
    // Headers
    //
    `include "modexpng_parameters.vh"


    //
    // Ports
    //
    input                                     clk;
    input                                     clk_bus;
    
    input                                     ena;
    input                                     wea;
    input  [BANK_ADDR_W + OP_ADDR_W     -1:0] addra;
    input  [              WORD_W        -1:0] dina;
    
    input                                     enb;
    input  [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] addrb;
    output [              BUS_DATA_W    -1:0] doutb;

    
    //
    // Memory
    //
    reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1];
   
    //
    // Write Port
    //
    wire [BANK_ADDR_W + BUS_OP_ADDR_W -2:0] addra_msb = addra[BANK_ADDR_W + BUS_OP_ADDR_W -1:1];
    wire                                    addra_lsb = addra[0];
    
    always @(posedge clk)
        //
        if (ena && wea) begin
           if (addra_lsb) mem[addra_msb][BUS_DATA_W-1:WORD_W] <= dina;
           else           mem[addra_msb][    WORD_W-1:     0] <= dina;
        end
            
    //
    // Read Port
    //
    reg [BUS_DATA_W -1:0] doutb_reg;
    
    assign doutb = doutb_reg;
        
    always @(posedge clk_bus)
        //
        if (enb)
            doutb_reg <= mem[addrb];
            
    
endmodule