rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v


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module modexpng_sdp_36k_x16_x32_wrapper_generic
(
    clk, clk_bus,
    
    ena, wea,
    addra, dina,
    
    enb, regceb,
    addrb, doutb
);


    //
    // Headers
    //
    `include "modexpng_parameters.vh"


    //
    // Ports
    //
    input                                     clk;
    input                                     clk_bus;
    
    input                                     ena;
    input                                     wea;
    input  [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] addra;
    input  [              BUS_DATA_W    -1:0] dina;
    
    input                                     enb;
    input                                     regceb;
    input  [BANK_ADDR_W + OP_ADDR_W     -1:0] addrb;
    output [              WORD_W        -1:0] doutb;

    
    //
    // Memory
    //
    reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1];
   
    //
    // Write Port
    //
    always @(posedge clk_bus)
        //
        if (ena && wea)
            mem[addra] <= dina;
            
    //
    // Read Port
    //
    reg [WORD_W -1:0] doutb_reg1;
    reg [WORD_W -1:0] doutb_reg2;
    
    assign doutb = doutb_reg2;
    
    wire [BUS_DATA_W -1:0] mem_addrb = mem[addrb[BANK_ADDR_W + OP_ADDR_W -1:1]];
    
    wire [    WORD_W -1:0] mem_addrb_msb = mem_addrb[ BUS_DATA_W -1:WORD_W];
    wire [    WORD_W -1:0] mem_addrb_lsb = mem_addrb[     WORD_W -1:     0];
    
    always @(posedge clk)
        //
        if (enb)
            doutb_reg1 <= addrb[0] ? mem_addrb_msb : mem_addrb_lsb;
            
    always @(posedge clk)
        //
        if (regceb)
            doutb_reg2 <= doutb_reg1;
    
    
endmodule