1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
|
//======================================================================
//
// Copyright (c) 2019, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module modexpng_recombinator_cell
(
clk,
ce, clr,
din, dout, dout_ext
);
//
// Headers
//
`include "modexpng_parameters.vh"
`include "modexpng_dsp48e1.vh"
`include "modexpng_dsp_slice_primitives.vh"
//
// Ports
//
input clk;
input ce;
input clr;
input [ MAC_W -1:0] din;
output [WORD_W -1:0] dout;
output [WORD_W :0] dout_ext;
//
// din <=> {z[13:0], y[15:0], x[15:0]}
//
wire [WORD_W -3:0] din_z = din[3 * WORD_W -3 : 2 * WORD_W]; // [45:32]
wire [WORD_W -1:0] din_y = din[2 * WORD_W -1 : WORD_W]; // [31:16]
wire [WORD_W -1:0] din_x = din[ WORD_W -1 : 0]; // [15: 0]
//
// Delayed Clock Enable
//
reg ce_dly = 1'b0;
always @(posedge clk) ce_dly <= ce;
//
// DSP Slice Buses
//
wire [DSP48E1_A_W-1:0] a_int;
wire [DSP48E1_B_W-1:0] b_int;
wire [DSP48E1_C_W-1:0] c_int;
wire [DSP48E1_P_W-1:0] p_int;
assign {a_int, b_int} = {{(DSP48E1_C_W-(2*WORD_W+1)){1'b0}}, din_z, din_y[WORD_W-1], din_y};
assign {c_int} = {{(DSP48E1_C_W-(2*WORD_W+1)){1'b0}}, WORD_ZERO, din_x[WORD_W-1], din_x};
//
// Combinational OPMODE Switch
//
reg [DSP48E1_OPMODE_W-1:0] opmode;
always @(clr)
//
case (clr)
1'b1: opmode = DSP48E1_OPMODE_Z0_YC_X0;
1'b0: opmode = DSP48E1_OPMODE_ZP17_YC_XAB;
endcase
//
// DSP Slice Instance
//
`MODEXPNG_DSP_SLICE_ADDSUB #(.AB_REG(2)) dsp_inst
(
.clk (clk),
.ce_ab1 (ce),
.ce_ab2 (ce_dly),
.ce_c (ce),
.ce_p (ce_dly),
.ce_ctrl (ce),
.ab ({a_int, b_int}),
.c (c_int),
.p (p_int),
.op_mode (opmode),
.alu_mode (DSP48E1_ALUMODE_Z_PLUS_X_AND_Y_AND_CIN),
.carry_in_sel (DSP48E1_CARRYINSEL_CARRYIN),
.casc_p_in (),
.casc_p_out (),
.carry_out ()
);
//
// Output Mapping
//
assign dout = {p_int[WORD_W-1:0]};
assign dout_ext = {p_int[WORD_W+1], dout};
endmodule
|
