1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
|
module modexpng_mmm_dout_addr
(
clk, rst_n,
//index_last,
fsm_state,
load_xy_addr,
load_addr_zero,
load_nn_coeff_addr_done,
/*
col_index_zero, col_index_next,*/
x_dout_addr, y_dout_addr,
x_dout_ena, y_dout_ena,
x_dout_bank, y_dout_bank
);
//
// Includes
//
`include "modexpng_parameters.vh"
`include "modexpng_parameters_x8.vh"
`include "modexpng_mmm_fsm.vh"
//
// Parameters
//
parameter INDEX_WIDTH = 6;
//
// Ports
//
input clk;
input rst_n;
//input [ INDEX_WIDTH-1:0] index_last;
input [FSM_STATE_WIDTH-1:0] fsm_state;
input [INDEX_WIDTH:0] load_xy_addr; // address
input load_addr_zero;
input load_nn_coeff_addr_done;
//input [ INDEX_WIDTH-4:0] col_index_zero;
//input [ INDEX_WIDTH-4:0] col_index_next;
output [INDEX_WIDTH-4:0] x_dout_addr;
output [INDEX_WIDTH-4:0] y_dout_addr;
output [NUM_MULTS-1:0] x_dout_ena;
output [NUM_MULTS-1:0] y_dout_ena;
output [3-1:0] x_dout_bank;
output [3-1:0] y_dout_bank;
//
// Registers
//
reg [INDEX_WIDTH-4:0] x_dout_addr_reg; //clog2
reg [INDEX_WIDTH-4:0] y_dout_addr_reg; //clog2
reg [NUM_MULTS-1:0] x_dout_ena_reg = {NUM_MULTS{1'b0}};
reg [NUM_MULTS-1:0] y_dout_ena_reg = {NUM_MULTS{1'b0}};
reg [NUM_MULTS-1:0] x_dout_ena_int;
reg [NUM_MULTS-1:0] y_dout_ena_int;
reg [3-1:0] x_dout_bank_reg;
reg [3-1:0] y_dout_bank_reg;
//
// Mapping
//
assign x_dout_addr = x_dout_addr_reg;
assign y_dout_addr = y_dout_addr_reg;
assign x_dout_ena = x_dout_ena_reg;
assign y_dout_ena = y_dout_ena_reg;
assign x_dout_bank = x_dout_bank_reg;
assign y_dout_bank = y_dout_bank_reg;
always @(posedge clk)
//
case (fsm_state)
//
FSM_STATE_LOAD_T1T2_3: begin
x_dout_addr_reg <= load_xy_addr[INDEX_WIDTH-1:3];
y_dout_addr_reg <= load_xy_addr[INDEX_WIDTH-1:3];
end
//
FSM_STATE_LOAD_NN_COEFF_3: begin
x_dout_addr_reg <= !load_nn_coeff_addr_done ? load_xy_addr[INDEX_WIDTH-1:3] : BANK_XY_AUX_ADDR_N_COEFF[INDEX_WIDTH-4:0];
y_dout_addr_reg <= !load_nn_coeff_addr_done ? load_xy_addr[INDEX_WIDTH-1:3] : BANK_XY_AUX_ADDR_N_COEFF[INDEX_WIDTH-4:0];
end
//
default: begin
x_dout_addr_reg <= {INDEX_WIDTH-3{1'bX}};
y_dout_addr_reg <= {INDEX_WIDTH-3{1'bX}};
end
//
endcase
wire [NUM_MULTS-1:0] load_xy_ena_init = {{NUM_MULTS-1{1'b0}}, 1'b1};
always @(posedge clk)
//
case (fsm_state)
//
FSM_STATE_LOAD_T1T2_2: begin
x_dout_ena_int <= load_addr_zero ? load_xy_ena_init : {x_dout_ena_int[NUM_MULTS-2:0], x_dout_ena_int[NUM_MULTS-1]};
y_dout_ena_int <= load_addr_zero ? load_xy_ena_init : {y_dout_ena_int[NUM_MULTS-2:0], y_dout_ena_int[NUM_MULTS-1]};
end
//
FSM_STATE_LOAD_NN_COEFF_2: begin
x_dout_ena_int <= load_addr_zero ? load_xy_ena_init : {x_dout_ena_int[NUM_MULTS-2:0], x_dout_ena_int[NUM_MULTS-1] & ~load_nn_coeff_addr_done};
y_dout_ena_int <= load_addr_zero ? load_xy_ena_init : {y_dout_ena_int[NUM_MULTS-2:0], y_dout_ena_int[NUM_MULTS-1]};
end
//
endcase
always @(posedge clk or negedge rst_n)
//
if (!rst_n) begin
x_dout_ena_reg <= {NUM_MULTS{1'b0}};
y_dout_ena_reg <= {NUM_MULTS{1'b0}};
end else case (fsm_state)
//
FSM_STATE_LOAD_T1T2_3,
FSM_STATE_LOAD_NN_COEFF_3: begin
x_dout_ena_reg <= x_dout_ena_int;
y_dout_ena_reg <= y_dout_ena_int;
end
//
default: begin
x_dout_ena_reg <= {NUM_MULTS{1'b0}};
y_dout_ena_reg <= {NUM_MULTS{1'b0}};
end
//
endcase
always @(posedge clk)
//
case (fsm_state)
//
FSM_STATE_LOAD_T1T2_3: begin
x_dout_bank_reg <= BANK_X_T1;
y_dout_bank_reg <= BANK_Y_T2;
end
//
FSM_STATE_LOAD_NN_COEFF_3: begin
x_dout_bank_reg <= !load_nn_coeff_addr_done ? BANK_X_N : BANK_XY_AUX;
y_dout_bank_reg <= !load_nn_coeff_addr_done ? BANK_Y_N_COEFF : BANK_XY_AUX;
end
//
default: begin
x_dout_bank_reg <= BANK_XY_ANY;
y_dout_bank_reg <= BANK_XY_ANY;
end
//
endcase
endmodule
|
