user/shatov/modexpng - "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA

Age	Commit message (Collapse)	Author
2020-01-20	Updated microcode source to match the changes made to general worker module.	Pavel V. Shatov (Meister)

2019-10-23	Added missing copyright headers.	Pavel V. Shatov (Meister)

2019-10-21	Reworked testbench, clk_sys and clk_core can now have any ratio, not	Pavel V. Shatov (Meister)
	necessarily 1:2. Fixed compile-time issue where ISE fails to place two DSP slices next to each other, if A and/or B cascade path(s) between then are partially connected. Basically, if cascade is used, entire bus must be connected.
2019-10-21	Added support for non-CRT mode. Further refactoring.	Pavel V. Shatov (Meister)

2019-10-21	Redesigned the testbench. Core clock does not necessarily need to be twice	Pavel V. Shatov (Meister)
	faster than the bus clock now. It can be the same, or say four times faster.
2019-10-21	Entire CRT signature algorithm works by now.	Pavel V. Shatov (Meister)
	Moved micro-operations handler into a separate module file, this way we don't have any synthesized stuff in the top-level module, just instantiations. This is more consistent from the design partitioning point of view. Btw, Xilinx claims their tools work better that way too, but who knows... Added optional simulation-only code to assist debugging. Un-comment the ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever try to synthesize the core with debugging enabled.
2019-10-21	Added the regular (not modular) addition operation required during the final	Pavel V. Shatov (Meister)
	step of the Garner's formula algorithm. Note, that the addition is "uneven" in the sense, that the first operand is full-size (as wide as the modulus), while the second one is only half the size. The adder internally banks the second input port during the second half of the addition.
2019-10-21	Added "MERGE_LH" micro-operation. To be able to do Garner's formula we need	Pavel V. Shatov (Meister)
	regular (not modular) multiplication. We're doing this by telling the modular multiplier to stop after the "square" step, which computes A*B. The problem is that the multiplier stores the lower part of the product in the internal bank L and the upper part in the internal bank H, but we need to be able to do operations on the product as a whole. MERGE_LH that combines the two halves of the product into one bank.
2019-10-21	Refactored general worker module	Pavel V. Shatov (Meister)
	Added modular subtraction micro-operation
2019-10-03	Added more micro-operations, entire Montgomery exponentiation ladder works now.	Pavel V. Shatov (Meister)

2019-10-03	Added more micro-operations, also added "general worker" module. The worker ↵	Pavel V. Shatov (Meister)
	is basically a block memory data mover, but it can also do some supporting operations required for the Garner's formula part of the exponentiation.
2019-10-03	Expanded micro-operation parameters (added dedicated control bit to force ↵	Pavel V. Shatov (Meister)
	the B input of the modular multiplier to 1, this is necessary to bring numbers out of Montgomery domain).
2019-10-03	Reworked storage architecture (moved I/O memory to a separate module, since ↵	Pavel V. Shatov (Meister)
	there's only one instance of input/output values, while storage manager has dual storage space for P and Q multipliers). Started working on microcoded layer, added input operation and modular multiplication.