| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-11-19 | Removed the latch accidentally created while pipelining the uOP engine module. | Pavel V. Shatov (Meister) |
| 2019-11-16 | The uOP engine didn't compile at 180 MHz. The pipeline had two stages: FETCH | Pavel V. Shatov (Meister) |
| 2019-10-23 | Added missing copyright headers. | Pavel V. Shatov (Meister) |
| 2019-10-23 | Added simulation-only code to measure multiplier load. | Pavel V. Shatov (Meister) |
| 2019-10-21 | Further work: | Pavel V. Shatov (Meister) |
| 2019-10-21 | Added support for non-CRT mode. Further refactoring. | Pavel V. Shatov (Meister) |
| 2019-10-21 | Entire CRT signature algorithm works by now. | Pavel V. Shatov (Meister) |
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index : user/shatov/modexpng | |
| "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA | git repositories |
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