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2019-10-23Added missing copyright headers.Pavel V. Shatov (Meister)
2019-10-21Entire CRT signature algorithm works by now.Pavel V. Shatov (Meister)
Moved micro-operations handler into a separate module file, this way we don't have any synthesized stuff in the top-level module, just instantiations. This is more consistent from the design partitioning point of view. Btw, Xilinx claims their tools work better that way too, but who knows... Added optional simulation-only code to assist debugging. Un-comment the ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever try to synthesize the core with debugging enabled.
2019-10-03Reworked storage architecture (moved I/O memory to a separate module, since ↵Pavel V. Shatov (Meister)
there's only one instance of input/output values, while storage manager has dual storage space for P and Q multipliers). Started working on microcoded layer, added input operation and modular multiplication.