| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-10-23 | Added missing copyright headers. | Pavel V. Shatov (Meister) | |
| 2019-10-21 | Entire CRT signature algorithm works by now. | Pavel V. Shatov (Meister) | |
| Moved micro-operations handler into a separate module file, this way we don't have any synthesized stuff in the top-level module, just instantiations. This is more consistent from the design partitioning point of view. Btw, Xilinx claims their tools work better that way too, but who knows... Added optional simulation-only code to assist debugging. Un-comment the ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever try to synthesize the core with debugging enabled. | |||
| 2019-10-01 | Redesigned core architecture, unified bank structure. All storage blocks now | Pavel V. Shatov (Meister) | |
| have eight 4kbit entries and occupy one 36K BRAM tile. | |||
| 2019-10-01 | Major rewrite (different core hierarchy, buses, wrappers, etc). | Pavel V. Shatov (Meister) | |
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index : user/shatov/modexpng | |
| "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA | git repositories |
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