user/shatov/modexpng - "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA

Age	Commit message (Collapse)	Author
2019-10-21	Reworked testbench, clk_sys and clk_core can now have any ratio, not	Pavel V. Shatov (Meister)
	necessarily 1:2. Fixed compile-time issue where ISE fails to place two DSP slices next to each other, if A and/or B cascade path(s) between then are partially connected. Basically, if cascade is used, entire bus must be connected.
2019-10-21	Further work:	Pavel V. Shatov (Meister)
	- added core wrapper - fixed module resets across entire core (all the resets are now consistently active-low) - continued refactoring
2019-10-21	Redesigned the testbench. Core clock does not necessarily need to be twice	Pavel V. Shatov (Meister)
	faster than the bus clock now. It can be the same, or say four times faster.
2019-10-03	Added more micro-operations, also added "general worker" module. The worker ↵	Pavel V. Shatov (Meister)
	is basically a block memory data mover, but it can also do some supporting operations required for the Garner's formula part of the exponentiation.
2019-10-01	Redesigned core architecture, unified bank structure. All storage blocks now	Pavel V. Shatov (Meister)
	have eight 4kbit entries and occupy one 36K BRAM tile.
2019-10-01	Major rewrite (different core hierarchy, buses, wrappers, etc).	Pavel V. Shatov (Meister)