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"Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA
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2020-01-21
Cosmetic change to easily switch tests on/off.
Pavel V. Shatov (Meister)
2019-10-23
Added missing copyright headers.
Pavel V. Shatov (Meister)
2019-10-23
Fixed all the testbenches to work with the latest RTL sources.
Pavel V. Shatov (Meister)
2019-10-21
Reworked testbench, clk_sys and clk_core can now have any ratio, not
Pavel V. Shatov (Meister)
2019-10-21
Further work:
Pavel V. Shatov (Meister)
2019-10-21
Added support for non-CRT mode. Further refactoring.
Pavel V. Shatov (Meister)
2019-10-21
Redesigned the testbench. Core clock does not necessarily need to be twice
Pavel V. Shatov (Meister)
2019-10-21
Entire CRT signature algorithm works by now.
Pavel V. Shatov (Meister)
2019-10-21
Refactored general worker module
Pavel V. Shatov (Meister)
2019-10-03
Added more micro-operations, entire Montgomery exponentiation ladder works now.
Pavel V. Shatov (Meister)
2019-10-01
Implemented the final stage of the Montgomery modular multiplication, i.e.
Pavel V. Shatov (Meister)
2019-10-01
Further work on the Montgomery modular multiplier. Added the third
Pavel V. Shatov (Meister)
2019-10-01
Further work on the Montgomery modular multiplier. Can now to the "triangular"
Pavel V. Shatov (Meister)
2019-10-01
Started working on the pipelined Montgomery modular multiplier. Currently can
Pavel V. Shatov (Meister)