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2020-01-20Updated uOP engine to match the changes made to the general worker modulePavel V. Shatov (Meister)
2020-01-20Updated microcode source to match the changes made to general worker module.Pavel V. Shatov (Meister)
2020-01-20Cosmetic fix that only involves debug output during simulation.Pavel V. Shatov (Meister)
2020-01-20Added two pairs of new wrappers.Pavel V. Shatov (Meister)
2020-01-20Removed old DSP wrappers.Pavel V. Shatov (Meister)
2020-01-20 * DSP slices now have two use modes: MULT and ADD/SUBPavel V. Shatov (Meister)
2020-01-16This commit modifies the REGULAR_ADD_UNEVEN micro-operation to use DSP slicesPavel V. Shatov (Meister)
2020-01-16Reworked modular subtraction micro-operation. Previously it used "two-pass"Pavel V. Shatov (Meister)
2020-01-16Turns out, fabric addition and subtraction in the general worker module arePavel V. Shatov (Meister)
2020-01-16Had to rework the general worker module to reach 180 MHz core clock. The modulePavel V. Shatov (Meister)
2019-11-26One more cosmetic fix.Pavel V. Shatov (Meister)
2019-11-26Cosmetic fix.Pavel V. Shatov (Meister)
2019-11-26Forgot to push minor cosmetic fix.Pavel V. Shatov (Meister)
2019-11-20Small change to the reductor module to try to get past 180 MHz. Previously BRAMPavel V. Shatov (Meister)
2019-11-19Removed the latch accidentally created while pipelining the uOP engine module.Pavel V. Shatov (Meister)
2019-11-18Refactored reductor module.Pavel V. Shatov (Meister)
2019-11-16The uOP engine didn't compile at 180 MHz. The pipeline had two stages: FETCHPavel V. Shatov (Meister)
2019-11-13Beautified the README.md, should look somewhat less nasty now.Pavel V. Shatov (Meister)
2019-10-23Added missing copyright headers.Pavel V. Shatov (Meister)
2019-10-23Added demo driver code for STM32.Pavel V. Shatov (Meister)
2019-10-23Added readme file.Pavel V. Shatov (Meister)
2019-10-23Fixed port width mismatch warning.Pavel V. Shatov (Meister)
2019-10-23Added simulation-only code to measure multiplier load.Pavel V. Shatov (Meister)
2019-10-23Fixed all the testbenches to work with the latest RTL sources.Pavel V. Shatov (Meister)
2019-10-21Reworked testbench, clk_sys and clk_core can now have any ratio, notPavel V. Shatov (Meister)
2019-10-21Further work:Pavel V. Shatov (Meister)
2019-10-21Added support for non-CRT mode. Further refactoring.Pavel V. Shatov (Meister)
2019-10-21Redesigned the testbench. Core clock does not necessarily need to be twicePavel V. Shatov (Meister)
2019-10-21Entire CRT signature algorithm works by now.Pavel V. Shatov (Meister)
2019-10-21Added the regular (not modular) addition operation required during the finalPavel V. Shatov (Meister)
2019-10-21Added "MERGE_LH" micro-operation. To be able to do Garner's formula we needPavel V. Shatov (Meister)
2019-10-21Refactored general worker modulePavel V. Shatov (Meister)
2019-10-03Added more micro-operations, entire Montgomery exponentiation ladder works now.Pavel V. Shatov (Meister)
2019-10-03Added more micro-operations, also added "general worker" module. The worker i...Pavel V. Shatov (Meister)
2019-10-03Expanded micro-operation parameters (added dedicated control bit to force the...Pavel V. Shatov (Meister)
2019-10-03Reworked storage architecture (moved I/O memory to a separate module, since t...Pavel V. Shatov (Meister)
2019-10-03Redesigned storage modules, added top-level module, added I/O storage space.Pavel V. Shatov (Meister)
2019-10-01Redesigned core architecture, unified bank structure. All storage blocks nowPavel V. Shatov (Meister)
2019-10-01Major rewrite (different core hierarchy, buses, wrappers, etc).Pavel V. Shatov (Meister)
2019-10-01Implemented the final stage of the Montgomery modular multiplication, i.e.Pavel V. Shatov (Meister)
2019-10-01Further work on the Montgomery modular multiplier. Added the thirdPavel V. Shatov (Meister)
2019-10-01Further work on the Montgomery modular multiplier. Can now to the "triangular"Pavel V. Shatov (Meister)
2019-10-01Started working on the pipelined Montgomery modular multiplier. Currently canPavel V. Shatov (Meister)
2019-10-01Moved to "modexpng_fpga_model" repo, this one was meant for Verilog.Pavel V. Shatov (Meister)
2019-08-19* More cleanup (got rid of .wide. and .narrow.)Pavel V. Shatov (Meister)
2019-08-19* MASSIVE CLEANUPPavel V. Shatov (Meister)
2019-08-19* Added more micro-operationsPavel V. Shatov (Meister)
2019-08-19* Started conversion of the model to use micro-operationsPavel V. Shatov (Meister)
2019-08-19* Added more debugging options:Pavel V. Shatov (Meister)
2019-04-04Intermediate version to fix recombinaton overflow bug.Pavel V. Shatov (Meister)