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2020-02-03Adapted to the changes in the DSP slice wrappers.Pavel V. Shatov (Meister)
2020-02-03Added new DSP slice OPMODEs for the new recombination algorithm.Pavel V. Shatov (Meister)
2020-02-03Updated DSP slice wrappers for the new partial product recombination algorithm:Pavel V. Shatov (Meister)
2020-02-03Better handling of debug output (no need to manally adjust word count anymore).Pavel V. Shatov (Meister)
2020-01-30Uniform testbenches.Pavel V. Shatov (Meister)
2020-01-30This commit accomodates the changes made to DSP slice wrappers and also fixesPavel V. Shatov (Meister)
2020-01-30Accomodate the changes to DSP slice wrappers.Pavel V. Shatov (Meister)
2020-01-30 * more consistent port namesPavel V. Shatov (Meister)
2020-01-30Cosmetic rename of FSM states.Pavel V. Shatov (Meister)
2020-01-21Bump version number.Pavel V. Shatov (Meister)
2020-01-21Cosmetic change to easily switch tests on/off.Pavel V. Shatov (Meister)
2020-01-21Refactored the MMM module, now uses meaningful constant names from the includePavel V. Shatov (Meister)
2020-01-21Refactored MMM recombinator module, accomodated the changes in DSP slicePavel V. Shatov (Meister)
2020-01-21Update DSP wrapper instance names.Pavel V. Shatov (Meister)
2020-01-21The I/O manager has to work in sync with the general worker module. Made thePavel V. Shatov (Meister)
2020-01-21Renumbered micro-operations.Pavel V. Shatov (Meister)
2020-01-21Refactored modular reductor module.Pavel V. Shatov (Meister)
2020-01-21Added more meaningful constants to avoid certain hardcoded numbers.Pavel V. Shatov (Meister)
2020-01-21Tiny cosmetic typo fix ("dst" -> "dsp")Pavel V. Shatov (Meister)
2020-01-20For the new general worker module to work we need dynamic switching of DSPPavel V. Shatov (Meister)
2020-01-20Updated uOP engine to match the changes made to the general worker modulePavel V. Shatov (Meister)
2020-01-20Updated microcode source to match the changes made to general worker module.Pavel V. Shatov (Meister)
2020-01-20Cosmetic fix that only involves debug output during simulation.Pavel V. Shatov (Meister)
2020-01-20Added two pairs of new wrappers.Pavel V. Shatov (Meister)
2020-01-20Removed old DSP wrappers.Pavel V. Shatov (Meister)
2020-01-20 * DSP slices now have two use modes: MULT and ADD/SUBPavel V. Shatov (Meister)
2020-01-16This commit modifies the REGULAR_ADD_UNEVEN micro-operation to use DSP slicesPavel V. Shatov (Meister)
2020-01-16Reworked modular subtraction micro-operation. Previously it used "two-pass"Pavel V. Shatov (Meister)
2020-01-16Turns out, fabric addition and subtraction in the general worker module arePavel V. Shatov (Meister)
2020-01-16Had to rework the general worker module to reach 180 MHz core clock. The modulePavel V. Shatov (Meister)
2019-11-26One more cosmetic fix.Pavel V. Shatov (Meister)
2019-11-26Cosmetic fix.Pavel V. Shatov (Meister)
2019-11-26Forgot to push minor cosmetic fix.Pavel V. Shatov (Meister)
2019-11-20Small change to the reductor module to try to get past 180 MHz. Previously BRAMPavel V. Shatov (Meister)
2019-11-19Removed the latch accidentally created while pipelining the uOP engine module.Pavel V. Shatov (Meister)
2019-11-18Refactored reductor module.Pavel V. Shatov (Meister)
2019-11-16The uOP engine didn't compile at 180 MHz. The pipeline had two stages: FETCHPavel V. Shatov (Meister)
2019-11-13Beautified the README.md, should look somewhat less nasty now.Pavel V. Shatov (Meister)
2019-10-23Added missing copyright headers.Pavel V. Shatov (Meister)
2019-10-23Added demo driver code for STM32.Pavel V. Shatov (Meister)
2019-10-23Added readme file.Pavel V. Shatov (Meister)
2019-10-23Fixed port width mismatch warning.Pavel V. Shatov (Meister)
2019-10-23Added simulation-only code to measure multiplier load.Pavel V. Shatov (Meister)
2019-10-23Fixed all the testbenches to work with the latest RTL sources.Pavel V. Shatov (Meister)
2019-10-21Reworked testbench, clk_sys and clk_core can now have any ratio, notPavel V. Shatov (Meister)
2019-10-21Further work:Pavel V. Shatov (Meister)
2019-10-21Added support for non-CRT mode. Further refactoring.Pavel V. Shatov (Meister)
2019-10-21Redesigned the testbench. Core clock does not necessarily need to be twicePavel V. Shatov (Meister)
2019-10-21Entire CRT signature algorithm works by now.Pavel V. Shatov (Meister)
2019-10-21Added the regular (not modular) addition operation required during the finalPavel V. Shatov (Meister)
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