user/shatov/modexpng - "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA

Age	Commit message (Collapse)	Author
2019-10-01	Implemented the final stage of the Montgomery modular multiplication, i.e.	Pavel V. Shatov (Meister)
	addition of AB and M then reduction by right-shift.
2019-10-01	Further work on the Montgomery modular multiplier. Added the third	Pavel V. Shatov (Meister)
	"rectangular" stage of the multiplication process, i.e. computation of how many copies of the modulus N to add to the intermediate product AB to zeroize the lower half: M = Q * N.
2019-10-01	Further work on the Montgomery modular multiplier. Can now to the "triangular"	Pavel V. Shatov (Meister)
	part of multiplication, i.e. compute the "magic" reduction coefficient Q = LSB(AB) * N_COEFF.
2019-10-01	Started working on the pipelined Montgomery modular multiplier. Currently can	Pavel V. Shatov (Meister)
	do the "square" part of the multiplication, i.e. compute the twice larger intermediate product AB = A * B.
2019-10-01	Moved to "modexpng_fpga_model" repo, this one was meant for Verilog.	Pavel V. Shatov (Meister)

2019-08-19	* More cleanup (got rid of .wide. and .narrow.)	Pavel V. Shatov (Meister)
	* Working microcode for non-CRT exponentiation (i.e. when only d is known)
2019-08-19	* MASSIVE CLEANUP	Pavel V. Shatov (Meister)
	* All the data buses are now either 16 or 18 bits wide for consistency * More consistent naming of micro-operations * More debugging options (can specify which ladder iteration to dump)
2019-08-19	* Added more micro-operations	Pavel V. Shatov (Meister)
	* Working microcode for CRT exponentiation * Further refactoring
2019-08-19	* Started conversion of the model to use micro-operations	Pavel V. Shatov (Meister)
	* Added initial operand bank structure (working "wide"/"narrow" pairs plus input & output banks). The core has four pairs of working banks (X.X and X.Y for Montgomery ladder with modulus P, Y.X and Y.Y for modulus Q)
2019-08-19	* Added more debugging options:	Pavel V. Shatov (Meister)
	- intentionally trigger internal overflow handler - dump MAC inputs - dump intermediate numbers during the reduction phase * Bus widths changes * Some cosmetic changes
2019-04-04	Intermediate version to fix recombinaton overflow bug.	Pavel V. Shatov (Meister)

2019-04-04	Fixed 4096-bit test vector generation.	Pavel V. Shatov (Meister)

2019-04-02	Removed some boilerplate code, all the three multiplication flavours are now	Pavel V. Shatov (Meister)
	working consistently. Still need to rework recombination routines.
2019-04-02	Cosmetic fixes.	Pavel V. Shatov (Meister)

2019-04-02	Same changes for "triangle" multiplication phase as for the "square" one	Pavel V. Shatov (Meister)
	(debugging output, simpler MAC clearing and index rotation logic).
2019-04-02	Rewrote "square" recombination to match how it works in hardware.	Pavel V. Shatov (Meister)

2019-03-30	* more debugging output	Pavel V. Shatov (Meister)
	* more precise modelling of DSP slice
2019-03-24	Simplified index calculation and accumulator clearing logic.	Pavel V. Shatov (Meister)
	Better debug printout of accumulators.
2019-03-23	Added optional output of intermediate quantities for debugging.	Pavel V. Shatov (Meister)
	Reworked index rotation code for better readability.
2019-03-23	Mutate blinding tuple.	Pavel V. Shatov (Meister)

2019-03-23	Added blinding into math model.	Pavel V. Shatov (Meister)

2019-03-23	ModExpNG ("Next Generation") math model.	Pavel V. Shatov (Meister)

2019-03-23	Updated readme file.	Pavel V. Shatov (Meister)

2019-03-23	Added blinding support to test vector generation scripts.	Pavel V. Shatov (Meister)

2019-03-23	Instructions on how to use the vector generation scripts.	Pavel V. Shatov (Meister)

2019-03-23	Don't track the test vector itself.	Pavel V. Shatov (Meister)

2019-03-23	Randomized test vector generation scripts for ModExpNG.	Pavel V. Shatov (Meister)