diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/modexpng_dsp_slice_addsub_wrapper_generic.v | 32 | ||||
| -rw-r--r-- | rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v | 31 |
2 files changed, 24 insertions, 39 deletions
diff --git a/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v b/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v index d5b294c..1c4ca00 100644 --- a/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v +++ b/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v @@ -30,15 +30,10 @@ // //====================================================================== -module modexpng_dsp_slice_addsub_wrapper_generic # -( - AB_REG = 1 -) +module modexpng_dsp_slice_addsub_wrapper_generic ( clk, - ce_ab1, - ce_ab2, - ce_c, + ce_abc, ce_p, ce_ctrl, ab, c, p, @@ -53,9 +48,7 @@ module modexpng_dsp_slice_addsub_wrapper_generic # `include "modexpng_dsp48e1.vh" input clk; - input ce_ab1; - input ce_ab2; - input ce_c; + input ce_abc; input ce_p; input ce_ctrl; input [ DSP48E1_C_W -1:0] ab; @@ -72,22 +65,19 @@ module modexpng_dsp_slice_addsub_wrapper_generic # // // Internal Registers // - reg [ DSP48E1_C_W -1:0] reg_ab1; - reg [ DSP48E1_C_W -1:0] reg_ab2; + reg [ DSP48E1_C_W -1:0] reg_ab; reg [ DSP48E1_C_W -1:0] reg_c; reg [ DSP48E1_OPMODE_W -1:0] reg_op_mode; reg [ DSP48E1_ALUMODE_W -1:0] reg_alu_mode; reg [DSP48E1_CARRYINSEL_W -1:0] reg_carry_in_sel; - always @(posedge clk) begin - // - if (ce_ab1) reg_ab1 <= ab; - if (ce_ab2) reg_ab2 <= AB_REG == 2 ? reg_ab1 : ab; - if (ce_c) reg_c <= c; + always @(posedge clk) // - end - + if (ce_abc) begin + reg_ab <= ab; + reg_c <= c; + end always @(posedge clk) // @@ -134,6 +124,8 @@ module modexpng_dsp_slice_addsub_wrapper_generic # input [DSP48E1_P_W-1:0] pcin_value; case (opmode_z) DSP48E1_OPMODE_Z_0: calc_mux_z = {DSP48E1_C_W{1'b0}}; // 000 + DSP48E1_OPMODE_Z_PCIN: calc_mux_z = pcin_value; // 001 + DSP48E1_OPMODE_Z_P: calc_mux_z = p_value; // 010 DSP48E1_OPMODE_Z_C: calc_mux_z = c_value; // 011 DSP48E1_OPMODE_Z_PCIN17: calc_mux_z = {{17{1'b0}}, pcin_value[DSP48E1_C_W-1:17]}; // 101 DSP48E1_OPMODE_Z_P17: calc_mux_z = {{17{1'b0}}, p_value[DSP48E1_C_W-1:17]}; // 110 @@ -215,7 +207,7 @@ module modexpng_dsp_slice_addsub_wrapper_generic # always @(posedge clk) // if (ce_p) {reg_carry_out, reg_p} <= - calc_p(reg_alu_mode, reg_op_mode, reg_carry_in_sel, reg_p, reg_ab2, reg_c, reg_carry_out, casc_p_in); + calc_p(reg_alu_mode, reg_op_mode, reg_carry_in_sel, reg_p, reg_ab, reg_c, reg_carry_out, casc_p_in); // diff --git a/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v b/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v index b8dcbce..2af6481 100644 --- a/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v +++ b/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v @@ -30,15 +30,10 @@ // //====================================================================== -module modexpng_dsp_slice_addsub_wrapper_xilinx # -( - AB_REG = 1 -) +module modexpng_dsp_slice_addsub_wrapper_xilinx ( clk, - ce_ab1, - ce_ab2, - ce_c, + ce_abc, ce_p, ce_ctrl, ab, c, p, @@ -53,9 +48,7 @@ module modexpng_dsp_slice_addsub_wrapper_xilinx # `include "modexpng_dsp48e1.vh" input clk; - input ce_ab1; - input ce_ab2; - input ce_c; + input ce_abc; input ce_p; input ce_ctrl; input [ DSP48E1_C_W -1:0] ab; @@ -81,15 +74,15 @@ module modexpng_dsp_slice_addsub_wrapper_xilinx # DSP48E1 # ( - .AREG (AB_REG), - .BREG (AB_REG), + .AREG (1), + .BREG (1), .CREG (1), .DREG (0), .ADREG (0), .MREG (0), .PREG (1), - .ACASCREG (AB_REG), - .BCASCREG (AB_REG), + .ACASCREG (1), + .BCASCREG (1), .INMODEREG (0), .OPMODEREG (1), .ALUMODEREG (1), @@ -115,12 +108,12 @@ module modexpng_dsp_slice_addsub_wrapper_xilinx # ( .CLK (clk), - .CEA1 (ce_ab1), - .CEB1 (ce_ab1), - .CEA2 (ce_ab2), - .CEB2 (ce_ab2), + .CEA1 (1'b0), + .CEB1 (1'b0), + .CEA2 (ce_abc), + .CEB2 (ce_abc), .CEAD (1'b0), - .CEC (ce_c), + .CEC (ce_abc), .CED (1'b0), .CEM (1'b0), .CEP (ce_p), |