diff options
Diffstat (limited to 'rtl/modexpng_io_block.v')
| -rw-r--r-- | rtl/modexpng_io_block.v | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/rtl/modexpng_io_block.v b/rtl/modexpng_io_block.v index 68d13c4..d7dd72e 100644 --- a/rtl/modexpng_io_block.v +++ b/rtl/modexpng_io_block.v @@ -84,13 +84,17 @@ module modexpng_io_block wire bus_data_wr_input_1 = bus_data_wr && (bus_addr_msb == 2'd0); wire bus_data_wr_input_2 = bus_data_wr && (bus_addr_msb == 2'd1); + wire bus_cs_input_1 = bus_cs && (bus_addr_msb == 2'b00); + wire bus_cs_input_2 = bus_cs && (bus_addr_msb == 2'b01); + wire bus_cs_output = bus_cs && (bus_addr_msb == 2'b10); + /* INPUT_1 */ modexpng_tdp_36k_x16_x32_wrapper bram_input_1 ( .clk (clk), // core clock .clk_bus (clk_bus), // bus clock - .ena (bus_cs), // bus side read-write + .ena (bus_cs_input_1), // bus side read-write .wea (bus_data_wr_input_1), // .addra (bus_addr_lsb), // .dina (bus_data_wr), // @@ -109,7 +113,7 @@ module modexpng_io_block .clk (clk), // core clock .clk_bus (clk_bus), // bus clock - .ena (bus_cs), // bus side write-only + .ena (bus_cs_input_2), // bus side write-only .wea (bus_data_wr_input_2), // .addra (bus_addr_lsb), // .dina (bus_data_wr), // @@ -132,7 +136,7 @@ module modexpng_io_block .addra (out_addr), // .dina (out_din), // - .enb (bus_cs), // bus side read-only + .enb (bus_cs_output), // bus side read-only .addrb (bus_addr_lsb), // .doutb (bus_data_rd_output) // ); |