diff options
Diffstat (limited to 'rtl/modexpng_dsp_slice_addsub_wrapper_generic.v')
| -rw-r--r-- | rtl/modexpng_dsp_slice_addsub_wrapper_generic.v | 38 |
1 files changed, 24 insertions, 14 deletions
diff --git a/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v b/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v index 0ef45fe..d5b294c 100644 --- a/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v +++ b/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v @@ -30,13 +30,18 @@ // //====================================================================== -module modexpng_dsp_slice_addsub_wrapper_generic +module modexpng_dsp_slice_addsub_wrapper_generic # +( + AB_REG = 1 +) ( clk, - ce_abc, + ce_ab1, + ce_ab2, + ce_c, ce_p, ce_ctrl, - x, y, p, + ab, c, p, op_mode, alu_mode, carry_in_sel, @@ -48,11 +53,13 @@ module modexpng_dsp_slice_addsub_wrapper_generic `include "modexpng_dsp48e1.vh" input clk; - input ce_abc; + input ce_ab1; + input ce_ab2; + input ce_c; input ce_p; input ce_ctrl; - input [ DSP48E1_C_W -1:0] x; - input [ DSP48E1_C_W -1:0] y; + input [ DSP48E1_C_W -1:0] ab; + input [ DSP48E1_C_W -1:0] c; output [ DSP48E1_P_W -1:0] p; input [ DSP48E1_OPMODE_W -1:0] op_mode; input [ DSP48E1_ALUMODE_W -1:0] alu_mode; @@ -65,19 +72,22 @@ module modexpng_dsp_slice_addsub_wrapper_generic // // Internal Registers // - reg [ DSP48E1_C_W -1:0] reg_x; - reg [ DSP48E1_C_W -1:0] reg_y; + reg [ DSP48E1_C_W -1:0] reg_ab1; + reg [ DSP48E1_C_W -1:0] reg_ab2; + reg [ DSP48E1_C_W -1:0] reg_c; reg [ DSP48E1_OPMODE_W -1:0] reg_op_mode; reg [ DSP48E1_ALUMODE_W -1:0] reg_alu_mode; reg [DSP48E1_CARRYINSEL_W -1:0] reg_carry_in_sel; - always @(posedge clk) + always @(posedge clk) begin // - if (ce_abc) begin - reg_x <= x; - reg_y <= y; - end + if (ce_ab1) reg_ab1 <= ab; + if (ce_ab2) reg_ab2 <= AB_REG == 2 ? reg_ab1 : ab; + if (ce_c) reg_c <= c; + // + end + always @(posedge clk) // @@ -205,7 +215,7 @@ module modexpng_dsp_slice_addsub_wrapper_generic always @(posedge clk) // if (ce_p) {reg_carry_out, reg_p} <= - calc_p(reg_alu_mode, reg_op_mode, reg_carry_in_sel, reg_p, reg_x, reg_y, reg_carry_out, casc_p_in); + calc_p(reg_alu_mode, reg_op_mode, reg_carry_in_sel, reg_p, reg_ab2, reg_c, reg_carry_out, casc_p_in); // |