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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-10-21 15:19:30 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-10-21 15:19:30 +0300
commitedd5efd83266bb534d7cde3d908e74749278ed96 (patch)
treec7b5295fc73f1904d9206630ca1eee897ba05cdc /stm32
parent584393ac5fc9bbe80887702ec2fc97bee999c5e7 (diff)
Reworked testbench, clk_sys and clk_core can now have any ratio, not
necessarily 1:2. Fixed compile-time issue where ISE fails to place two DSP slices next to each other, if A and/or B cascade path(s) between then are partially connected. Basically, if cascade is used, entire bus must be connected.
Diffstat (limited to 'stm32')
0 files changed, 0 insertions, 0 deletions