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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-01-20 23:44:15 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-01-20 23:44:15 +0300 |
| commit | b985d4516f1e739be0ea0dabb66da0bbeb5c8f86 (patch) | |
| tree | 12902b5d93465a09d02d0452510ead35db928c50 /stm32 | |
| parent | ab061afd20523bdb0342613f4eb343daee6571c6 (diff) | |
* DSP slices now have two use modes: MULT and ADD/SUB
* cosmetic rename of Verilog include file
Diffstat (limited to 'stm32')
0 files changed, 0 insertions, 0 deletions