This commit accomodates the changes made to DSP slice wrappers and also fixes

the subtle math overflow bug introduced while switching to DSP-based partial
multiplication product recombination.

2 files changed, 45 insertions, 46 deletions

diff --git a/rtl/modexpng_recombinator_block.v b/rtl/modexpng_recombinator_block.v
index f6e23e5..cc89db0 100644
--- a/rtl/modexpng_recombinator_block.v
+++ b/rtl/modexpng_recombinator_block.v
@@ -499,7 +499,7 @@ module modexpng_recombinator_block
     reg  [ 2:0] rcmb_xy_lsb_ce_purge = 3'b000;
     wire        rcmb_xy_lsb_ce_combined = rcmb_xy_lsb_ce | rcmb_xy_lsb_ce_aux | rcmb_xy_lsb_ce_purge[0];
     reg         rcmb_xy_lsb_clr;
-    wire        rcmb_xy_lsb_cry = !rcmb_xy_lsb_ce_purge[2] && (rcmb_xy_lsb_ce_purge[1] || rcmb_xy_lsb_ce_purge[0]);
+    wire        rcmb_xy_lsb_cry = !xy_valid_latch_lsb && rcmb_xy_lsb_ce_purge[1];
 
     reg  [ MAC_W     -1:0] rcmb_x_lsb_din;
     reg  [ MAC_W     -1:0] rcmb_y_lsb_din;
@@ -523,8 +523,6 @@ module modexpng_recombinator_block
         .clk      (clk),
         .ce       (rcmb_xy_lsb_ce_combined),
         .clr      (rcmb_xy_lsb_clr),
-        .cry      (rcmb_xy_lsb_cry),
-        .cin      (rcmb_x_msb_carry_1),
         .din      (rcmb_x_lsb_din),
         .dout     (rcmb_x_lsb_dout),
         .dout_ext (rcmb_x_lsb_dout_ext)
@@ -534,8 +532,6 @@ module modexpng_recombinator_block
         .clk      (clk),
         .ce       (rcmb_xy_lsb_ce_combined),
         .clr      (rcmb_xy_lsb_clr),
-        .cry      (rcmb_xy_lsb_cry),
-        .cin      (rcmb_y_msb_carry_1),
         .din      (rcmb_y_lsb_din),
         .dout     (rcmb_y_lsb_dout),
         .dout_ext (rcmb_y_lsb_dout_ext)
@@ -546,20 +542,15 @@ module modexpng_recombinator_block
         .clk      (clk),
         .ce       (rcmb_xy_msb_ce_combined),
         .clr      (rcmb_xy_msb_clr),
-        .cry      (1'b0),
-        .cin      (WORD_ZERO),
         .din      (rcmb_x_msb_din),
         .dout     (rcmb_x_msb_dout),
         .dout_ext ()
     );
-    
     modexpng_recombinator_cell recomb_y_msb
     (
         .clk      (clk),
         .ce       (rcmb_xy_msb_ce_combined),
         .clr      (rcmb_xy_msb_clr),
-        .cry      (1'b0),
-        .cin      (WORD_ZERO),
         .din      (rcmb_y_msb_din),
         .dout     (rcmb_y_msb_dout),
         .dout_ext ()
@@ -597,6 +588,9 @@ module modexpng_recombinator_block
         end else if (xy_aux_latch_lsb) begin
             rcmb_x_lsb_din <= dsp_x_p_latch[NUM_MULTS_AUX-1];
             rcmb_y_lsb_din <= dsp_y_p_latch[NUM_MULTS_AUX-1];
+        end else if (rcmb_xy_lsb_cry) begin
+            rcmb_x_lsb_din <= rcmb_x_msb_carry_1;
+            rcmb_y_lsb_din <= rcmb_y_msb_carry_1;
         end else begin
             rcmb_x_lsb_din <= {MAC_W{1'b0}};
             rcmb_y_lsb_din <= {MAC_W{1'b0}};
@@ -891,16 +885,26 @@ module modexpng_recombinator_block
         end
     endtask
          
-    task shift_rcmb_msb_carry;
+    task _update_rcmb_msb_carry;
         input [WORD_W -1:0] dout_x;
         input [WORD_W -1:0] dout_y;
         begin
             rcmb_x_msb_carry_0 <= dout_x;
             rcmb_y_msb_carry_0 <= dout_y;
             rcmb_x_msb_carry_1 <= rcmb_x_msb_carry_0;
-            rcmb_y_msb_carry_1 <= rcmb_y_msb_carry_0;
+            rcmb_y_msb_carry_1 <= rcmb_y_msb_carry_0;        
         end
     endtask
+         
+    task push_rcmb_msb_carry;
+        input [WORD_W -1:0] dout_x;
+        input [WORD_W -1:0] dout_y;
+        _update_rcmb_msb_carry(dout_x, dout_y);
+    endtask
+
+    task pop_rcmb_msb_carry;
+        _update_rcmb_msb_carry(WORD_DNC, WORD_DNC);
+    endtask
     
     task _update_wide;
         input [BANK_ADDR_W -1:0] bank;
@@ -1057,7 +1061,7 @@ module modexpng_recombinator_block
     //
     // Handy Signal
     //
-    wire [1:0] rcmb_xy_valid = {rcmb_xy_msb_valid, rcmb_xy_lsb_valid}; 
+    wire [1:0] rcmb_xy_valid = {rcmb_xy_msb_valid, rcmb_xy_lsb_valid};
 
 
     //
@@ -1095,13 +1099,11 @@ module modexpng_recombinator_block
                 //
                 2'b00: if (rcmb_msb_flag_delay_2) advance_rcmb_msb_delay(WORD_DNC, WORD_DNC, OP_ADDR_ZERO, 1'b0);
                 //
-                2'b01: if (rcmb_xy_lsb_cry)       shift_rcmb_msb_carry(WORD_DNC, WORD_DNC);
+                2'b01: if (rcmb_xy_lsb_cry)       pop_rcmb_msb_carry;
                 //
-                2'b10: if (cnt_msb < OP_ADDR_TWO) shift_rcmb_msb_carry(rcmb_x_msb_dout, rcmb_y_msb_dout);
+                2'b10: if (cnt_msb < OP_ADDR_TWO) push_rcmb_msb_carry(rcmb_x_msb_dout, rcmb_y_msb_dout);
                 //
-                2'b11: begin                      advance_rcmb_msb_delay(rcmb_x_msb_dout, rcmb_y_msb_dout, cnt_msb, 1'b1);
-                       if (rcmb_xy_lsb_cry)       shift_rcmb_msb_carry(WORD_DNC, WORD_DNC);
-                       end
+                2'b11:                            advance_rcmb_msb_delay(rcmb_x_msb_dout, rcmb_y_msb_dout, cnt_msb, 1'b1);
                 //
             endcase
             //        
@@ -1173,10 +1175,10 @@ module modexpng_recombinator_block
                 //
                 2'b00: if (rcmb_msb_flag_delay_2)                       advance_rcmb_msb_delay(WORD_DNC, WORD_DNC, OP_ADDR_ZERO, 1'b0);
                 //
-                2'b01: if (rcmb_xy_lsb_cry)                             shift_rcmb_msb_carry(WORD_DNC, WORD_DNC);
+                2'b01: if (rcmb_xy_lsb_cry)                             pop_rcmb_msb_carry;
                 //
                 2'b10: begin 
-                       if ((cnt_msb < OP_ADDR_TWO) && !cnt_msb_wrapped) shift_rcmb_msb_carry(rcmb_x_msb_dout, rcmb_y_msb_dout);
+                       if ((cnt_msb < OP_ADDR_TWO) && !cnt_msb_wrapped) push_rcmb_msb_carry(rcmb_x_msb_dout, rcmb_y_msb_dout);
                        if (cnt_msb_wrapped)                             advance_rcmb_msb_delay(WORD_DNC, WORD_DNC, OP_ADDR_ZERO, 1'b0);
                        end
                 //
diff --git a/rtl/modexpng_recombinator_cell.v b/rtl/modexpng_recombinator_cell.v
index 9761d9c..45fc68c 100644
--- a/rtl/modexpng_recombinator_cell.v
+++ b/rtl/modexpng_recombinator_cell.v
@@ -33,8 +33,7 @@
 module modexpng_recombinator_cell
 (
     clk,
-    ce, clr, cry,
-    cin,
+    ce, clr,
     din, dout, dout_ext
 );
 
@@ -53,8 +52,6 @@ module modexpng_recombinator_cell
     input                clk;
     input                ce;
     input                clr;
-    input                cry;
-    input  [WORD_W -1:0] cin;
     input  [ MAC_W -1:0] din;
     output [WORD_W -1:0] dout;
     output [WORD_W   :0] dout_ext;
@@ -83,42 +80,42 @@ module modexpng_recombinator_cell
     wire [DSP48E1_C_W-1:0] c_int;
     wire [DSP48E1_P_W-1:0] p_int;
 
-    assign {a_int, b_int} = {{(DSP48E1_C_W-WORD_W){1'b0}}, cin};
-    assign {c_int}        = {din_z, 1'b0, din_y, 1'b1, din_x};
-    
+    assign {a_int, b_int} = {{(DSP48E1_C_W-(2*WORD_W+1)){1'b0}},     din_z, din_y[WORD_W-1], din_y};
+    assign {c_int}        = {{(DSP48E1_C_W-(2*WORD_W+1)){1'b0}}, WORD_ZERO, din_x[WORD_W-1], din_x};
     
     //
     // Combinational OPMODE Switch
     //
     reg [DSP48E1_OPMODE_W-1:0] opmode;
     
-    always @(clr, cry)
+    always @(clr)
         //
-        casez ({clr, cry})  // clr has priority over cry!
-            2'b1?: opmode = DSP48E1_OPMODE_Z0_YC_X0;
-            2'b00: opmode = DSP48E1_OPMODE_ZP17_YC_X0;
-            2'b01: opmode = DSP48E1_OPMODE_ZP17_YC_XAB;
+        case (clr)
+            1'b1: opmode = DSP48E1_OPMODE_Z0_YC_X0;
+            1'b0: opmode = DSP48E1_OPMODE_ZP17_YC_XAB;
         endcase
 
 
     //
     // DSP Slice Instance
     //
-    `MODEXPNG_DSP_SLICE_ADDSUB dsp_inst
+    `MODEXPNG_DSP_SLICE_ADDSUB #(.AB_REG(2)) dsp_inst
     (
-        .clk          (clk),
-        .ce_abc       (ce),
-        .ce_p         (ce_dly),
-        .ce_ctrl      (ce),
-        .x            ({a_int, b_int}),
-        .y            (c_int),
-        .p            (p_int),
-        .op_mode      (opmode),
-        .alu_mode     (DSP48E1_ALUMODE_Z_PLUS_X_AND_Y_AND_CIN),
-        .carry_in_sel (DSP48E1_CARRYINSEL_CARRYIN),
-        .casc_p_in    (),
-        .casc_p_out   (),
-        .carry_out    ()
+        .clk            (clk),
+        .ce_ab1         (ce),
+        .ce_ab2         (ce_dly),
+        .ce_c           (ce),
+        .ce_p           (ce_dly),
+        .ce_ctrl        (ce),
+        .ab             ({a_int, b_int}),
+        .c              (c_int),
+        .p              (p_int),
+        .op_mode        (opmode),
+        .alu_mode       (DSP48E1_ALUMODE_Z_PLUS_X_AND_Y_AND_CIN),
+        .carry_in_sel   (DSP48E1_CARRYINSEL_CARRYIN),
+        .casc_p_in      (),
+        .casc_p_out     (),
+        .carry_out      ()
     );