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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-01-20 23:44:15 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-01-20 23:44:15 +0300
commitb985d4516f1e739be0ea0dabb66da0bbeb5c8f86 (patch)
tree12902b5d93465a09d02d0452510ead35db928c50 /rtl
parentab061afd20523bdb0342613f4eb343daee6571c6 (diff)
* DSP slices now have two use modes: MULT and ADD/SUB
* cosmetic rename of Verilog include file
Diffstat (limited to 'rtl')
-rw-r--r--rtl/modexpng_dsp_slice_primitives.vh (renamed from rtl/modexpng_dsp_slice_primitive.vh)6
1 files changed, 4 insertions, 2 deletions
diff --git a/rtl/modexpng_dsp_slice_primitive.vh b/rtl/modexpng_dsp_slice_primitives.vh
index 20a0b8f..be20e9e 100644
--- a/rtl/modexpng_dsp_slice_primitive.vh
+++ b/rtl/modexpng_dsp_slice_primitives.vh
@@ -32,10 +32,12 @@
`ifndef MODEXPNG_ENABLE_DEBUG
-`define MODEXPNG_DSP_SLICE modexpng_dsp_slice_wrapper_xilinx
+`define MODEXPNG_DSP_SLICE_MULT modexpng_dsp_slice_mult_wrapper_xilinx
+`define MODEXPNG_DSP_SLICE_ADDSUB modexpng_dsp_slice_addsub_wrapper_xilinx
`else
-`define MODEXPNG_DSP_SLICE modexpng_dsp_slice_wrapper_generic
+`define MODEXPNG_DSP_SLICE_MULT modexpng_dsp_slice_mult_wrapper_generic
+`define MODEXPNG_DSP_SLICE_ADDSUB modexpng_dsp_slice_addsub_wrapper_generic
`endif