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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-10-23 17:00:44 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-10-23 17:00:44 +0300
commit88f46be9bf792d5217dffcd91b0038576a1e3caa (patch)
tree2cc57e4ec409d3d6549a38d194040f4f4b9f86dc /rtl
parent657678ac85785aedeb53001ec4e5d2813cd5270a (diff)
Fixed port width mismatch warning.
Diffstat (limited to 'rtl')
-rw-r--r--rtl/modexpng_dsp_slice_wrapper_generic.v109
1 files changed, 6 insertions, 103 deletions
diff --git a/rtl/modexpng_dsp_slice_wrapper_generic.v b/rtl/modexpng_dsp_slice_wrapper_generic.v
index 7183d74..ad4e5e5 100644
--- a/rtl/modexpng_dsp_slice_wrapper_generic.v
+++ b/rtl/modexpng_dsp_slice_wrapper_generic.v
@@ -30,15 +30,15 @@ module modexpng_dsp_slice_wrapper_generic #
input [ DSP48E1_INMODE_W -1:0] inmode; //
input [ DSP48E1_OPMODE_W -1:0] opmode; //
input [DSP48E1_ALUMODE_W -1:0] alumode; //
- input [ WORD_EXT_W -1:0] casc_a_in; //
- input [ WORD_W -1:0] casc_b_in; //
- output [ WORD_EXT_W -1:0] casc_a_out; //
- output [ WORD_W -1:0] casc_b_out; //
+ input [ DSP48E1_A_W -1:0] casc_a_in; //
+ input [ DSP48E1_B_W -1:0] casc_b_in; //
+ output [ DSP48E1_A_W -1:0] casc_a_out; //
+ output [ DSP48E1_B_W -1:0] casc_b_out; //
//
// A Port
//
- wire [WORD_EXT_W -1:0] a_mux = AB_INPUT == "DIRECT" ? a : casc_a_in;
+ wire [WORD_EXT_W -1:0] a_mux = AB_INPUT == "DIRECT" ? a : casc_a_in[WORD_EXT_W-1:0];
reg [WORD_EXT_W -1:0] a_reg1;
reg [WORD_EXT_W -1:0] a_reg2;
@@ -52,7 +52,7 @@ module modexpng_dsp_slice_wrapper_generic #
//
// B Port
//
- wire [WORD_W -1:0] b_mux = AB_INPUT == "DIRECT" ? b : casc_b_in;
+ wire [WORD_W -1:0] b_mux = AB_INPUT == "DIRECT" ? b : casc_b_in[WORD_W-1:0];
reg [WORD_W -1:0] b_reg1;
reg [WORD_W -1:0] b_reg2;
@@ -88,102 +88,5 @@ module modexpng_dsp_slice_wrapper_generic #
if (ce_m) m_reg <= a_pad * b_pad;
if (ce_p) p_reg <= m_reg + p_pad;
end
-
-
- /*
- DSP48E1 #
- (
- .AREG (2),
- .BREG (B_REG),
- .CREG (0),
- .DREG (0),
- .ADREG (0),
- .MREG (1),
- .PREG (1),
- .ACASCREG (1),
- .BCASCREG (1),
- .INMODEREG (0),
- .OPMODEREG (1),
- .ALUMODEREG (0),
- .CARRYINREG (0),
- .CARRYINSELREG (0),
-
- .A_INPUT (AB_INPUT),
- .B_INPUT (AB_INPUT),
-
- .USE_DPORT ("FALSE"),
- .USE_MULT ("DYNAMIC"),
- .USE_SIMD ("ONE48"),
-
- .MASK ({DSP48E1_P_W{1'b1}}),
- .PATTERN ({DSP48E1_P_W{1'b0}}),
- .SEL_MASK ("MASK"),
- .SEL_PATTERN ("PATTERN"),
-
- .USE_PATTERN_DETECT ("NO_PATDET"),
- .AUTORESET_PATDET ("NO_RESET")
- )
- DSP48E1_inst
- (
- .CLK (clk),
-
- .CEA1 (ce_a1),
- .CEB1 (ce_b1),
- .CEA2 (ce_a2),
- .CEB2 (ce_b2),
- .CEAD (1'b0),
- .CEC (1'b0),
- .CED (1'b0),
- .CEM (ce_m),
- .CEP (ce_p),
- .CEINMODE (1'b0),
- .CECTRL (ce_mode),
- .CEALUMODE (1'b0),
- .CECARRYIN (1'b0),
-
- .A ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, a}),
- .B ({{(DSP48E1_B_W-WORD_W){1'b0}}, b}),
- .C ({DSP48E1_C_W{1'b0}}),
- .D ({DSP48E1_D_W{1'b0}}),
- .P ({p_dummy, p}),
-
- .INMODE (inmode),
- .OPMODE (opmode),
- .ALUMODE (alumode),
-
- .ACIN ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, casc_a_in}),
- .BCIN ({{(DSP48E1_B_W-WORD_W){1'b0}}, casc_b_in}),
- .ACOUT ({casc_a_dummy, casc_a_out}),
- .BCOUT ({casc_b_dummy, casc_b_out}),
- .PCIN ({DSP48E1_P_W{1'b0}}),
- .PCOUT (),
- .CARRYCASCIN (1'b0),
- .CARRYCASCOUT (),
-
- .RSTA (1'b0),
- .RSTB (1'b0),
- .RSTC (1'b0),
- .RSTD (1'b0),
- .RSTM (1'b0),
- .RSTP (1'b0),
- .RSTINMODE (1'b0),
- .RSTCTRL (1'b0),
- .RSTALUMODE (1'b0),
- .RSTALLCARRYIN (1'b0),
-
- .UNDERFLOW (),
- .OVERFLOW (),
- .PATTERNDETECT (),
- .PATTERNBDETECT (),
-
- .CARRYIN (1'b0),
- .CARRYOUT (),
- .CARRYINSEL (3'b000),
-
- .MULTSIGNIN (1'b0),
- .MULTSIGNOUT ()
- );
- */
-
endmodule