Had to rework the general worker module to reach 180 MHz core clock. The module

is responsible for doing certain supporting operations (mostly moving operands
between banks and doing some simple math operations, such as modular
subtraction and regular addition). Depending on the particular operation, one
of three bank address space sweep patterns was used:
 * one-pass (for things like carry propagation)
 * two-pass (for things like modular subtraction that produce intermediate
   values in the process)
 * one-pass interleaved (for copying when only either CRT_?.X or CRT_?.Y is
   rewritten: we can only write to X and Y simultaneously, so we have to
   interleave reads from the source bank with reads from the destination bank
   and overwrite the destination with its just read value, otherwise the second
   destination operand is lost)
I initially coded three FSMs, one for each of the address space sweeps and
triggered one of them depending on the opcode, but that turned out too
complicated. There's now only one FSM that always does the "one-pass
interleaved" pattern, whereas the second read (from the destination bank) is
inhibited when not need by the opcode.

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