diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 12:56:30 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 12:56:30 +0300 |
| commit | 9eac252242c69e51a38a9a88c87b564dd40b6257 (patch) | |
| tree | ab6653950a7f2a811598c73f15116fa5c009ec5c /rtl/modexpng_io_block.v | |
| parent | 36339014ec3d3ad3bb4622392d5075d674e7dbeb (diff) | |
Entire CRT signature algorithm works by now.
Moved micro-operations handler into a separate module file, this way we don't
have any synthesized stuff in the top-level module, just instantiations. This
is more consistent from the design partitioning point of view. Btw, Xilinx
claims their tools work better that way too, but who knows...
Added optional simulation-only code to assist debugging. Un-comment the
ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever
try to synthesize the core with debugging enabled.
Diffstat (limited to 'rtl/modexpng_io_block.v')
| -rw-r--r-- | rtl/modexpng_io_block.v | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/rtl/modexpng_io_block.v b/rtl/modexpng_io_block.v index d7dd72e..06ce2b1 100644 --- a/rtl/modexpng_io_block.v +++ b/rtl/modexpng_io_block.v @@ -26,6 +26,7 @@ module modexpng_io_block // Headers // `include "modexpng_parameters.vh" + `include "modexpng_storage_primitives.vh" // @@ -81,21 +82,21 @@ module modexpng_io_block wire [ BUS_DATA_W -1:0] bus_data_rd_input_1; wire [ BUS_DATA_W -1:0] bus_data_rd_output; - wire bus_data_wr_input_1 = bus_data_wr && (bus_addr_msb == 2'd0); - wire bus_data_wr_input_2 = bus_data_wr && (bus_addr_msb == 2'd1); + wire bus_we_input_1 = bus_we && (bus_addr_msb == 2'd0); + wire bus_we_input_2 = bus_we && (bus_addr_msb == 2'd1); wire bus_cs_input_1 = bus_cs && (bus_addr_msb == 2'b00); wire bus_cs_input_2 = bus_cs && (bus_addr_msb == 2'b01); wire bus_cs_output = bus_cs && (bus_addr_msb == 2'b10); /* INPUT_1 */ - modexpng_tdp_36k_x16_x32_wrapper bram_input_1 + `MODEXPNG_TDP_36K_X16_X32 bram_input_1 ( .clk (clk), // core clock .clk_bus (clk_bus), // bus clock .ena (bus_cs_input_1), // bus side read-write - .wea (bus_data_wr_input_1), // + .wea (bus_we_input_1), // .addra (bus_addr_lsb), // .dina (bus_data_wr), // .douta (bus_data_rd_input_1), // @@ -108,13 +109,13 @@ module modexpng_io_block /* INPUT_2 */ - modexpng_sdp_36k_x16_x32_wrapper bram_input_2 + `MODEXPNG_SDP_36K_X16_X32 bram_input_2 ( .clk (clk), // core clock .clk_bus (clk_bus), // bus clock .ena (bus_cs_input_2), // bus side write-only - .wea (bus_data_wr_input_2), // + .wea (bus_we_input_2), // .addra (bus_addr_lsb), // .dina (bus_data_wr), // @@ -126,7 +127,7 @@ module modexpng_io_block /* OUTPUT */ - modexpng_sdp_36k_x32_x16_wrapper bram_output + `MODEXPNG_SDP_36K_X32_X16 bram_output ( .clk (clk), // core clock .clk_bus (clk_bus), // bus clock |