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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-11-16 01:17:02 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-11-16 01:17:02 +0300
commitf4771a7b6774a53cbada5b86701d65e08a36c10d (patch)
treea8a54d115a178b1463bcedc6c37759d9acf33e9f /rtl/modexpng_dsp_array_block.v
parent65bf05440677643d9c1f2ae6a0573315f52926c8 (diff)
The uOP engine didn't compile at 180 MHz. The pipeline had two stages: FETCH
and DECODE. Apparently one clock cycle is not enough to entirely decode an instruction, so decoding now takes two clock cycles (DECODE_1 and DECODE_2). This seems to solve the problem. If we run into more timing violations here, we can add an extra DECODE_3 cycle and register the currently combinatorial uop_opcode_* flags at DECODE_2. This fix increases the core's latency by 59/32 clock cycles (CRT/non-CRT mode) plus two extra clock cycles per each bit of the exponent.
Diffstat (limited to 'rtl/modexpng_dsp_array_block.v')
0 files changed, 0 insertions, 0 deletions