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author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-03 16:38:18 +0300 |
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committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-03 16:38:18 +0300 |
commit | 0b4b42da734c1164b65a334351274f946b2d4dcb (patch) | |
tree | 5c4fc8a8b09ca962aa4335577fe3cf3a66ffcaff /rtl/modexpng_core_top.v | |
parent | 71f70252dfc7e41103dde420a721be8aa48486d5 (diff) |
Redesigned storage modules, added top-level module, added I/O storage space.
Diffstat (limited to 'rtl/modexpng_core_top.v')
-rw-r--r-- | rtl/modexpng_core_top.v | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/rtl/modexpng_core_top.v b/rtl/modexpng_core_top.v new file mode 100644 index 0000000..e834d37 --- /dev/null +++ b/rtl/modexpng_core_top.v @@ -0,0 +1,41 @@ +module modexpng_core_top +( + clk, clk_bus, + rst, + next, valid, + word_index_last, + bus_cs, + bus_we, + bus_addr, + bus_data_wr, + bus_data_rd +); + + + // + // Headers + // + `include "modexpng_parameters.vh" + + + // + // Ports + // + input clk; + input clk_bus; + + input rst; + + input next; + output valid; + + input bus_cs; + input bus_we; + input [4 * (BANK_ADDR_W + BUS_OP_ADDR_W) -1:0] bus_addr; + input [ BUS_DATA_W -1:0] bus_data_wr; + output [ BUS_DATA_W -1:0] bus_data_rd; + + + + +endmodule |