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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-10-01 16:18:33 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2019-10-01 16:18:33 +0300
commit71f70252dfc7e41103dde420a721be8aa48486d5 (patch)
tree182c413b590d6056b02c5d20818c3385c83610e3 /bench
parentfde62e373fdfcefefb7da10757a3db933160c911 (diff)
Redesigned core architecture, unified bank structure. All storage blocks now
have eight 4kbit entries and occupy one 36K BRAM tile.
Diffstat (limited to 'bench')
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