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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-11-19 13:05:02 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-11-19 13:05:02 +0300 |
| commit | 189dfd62e2385aa2f36c6283628b8d9285c49647 (patch) | |
| tree | 0c1c4e314b224fff447a384c959917509d5e0148 /bench/tb_core_full_1024.v | |
| parent | 863cac90f320d6b7587177bc2df798c611fe510b (diff) | |
Removed the latch accidentally created while pipelining the uOP engine module.
The FSM previously had four states encoded using two bits, so the next state
logic didn't have a default case, since all the possible states were used.
Addition of the fifth state required one more state bit, so the FSM now has
five states out eight possible and a default case is thus necessary.
Diffstat (limited to 'bench/tb_core_full_1024.v')
0 files changed, 0 insertions, 0 deletions