path: root/rtl/modexpng_dsp_slice_wrapper_generic.v

module modexpng_dsp_slice_wrapper_generic #
(
    AB_INPUT   = "DIRECT",
    B_REG      = 2
)
(
    clk,
    ce_a1, ce_b1, ce_a2, ce_b2,
    ce_m, ce_p, ce_mode,
    a, b, p,
    inmode, opmode, alumode,
    casc_a_in,  casc_b_in,
    casc_a_out, casc_b_out
);

    `include "modexpng_parameters.vh"
    `include "modexpng_dsp48e1.vh"
        
    input                           clk;            //
    input                           ce_a1;          //
    input                           ce_b1;          //
    input                           ce_a2;          //
    input                           ce_b2;          //
    input                           ce_m;           //
    input                           ce_p;           //
    input                           ce_mode;        //
    input  [       WORD_EXT_W -1:0] a;              //
    input  [           WORD_W -1:0] b;              //
    output [            MAC_W -1:0] p;              //
    input  [ DSP48E1_INMODE_W -1:0] inmode;         //
    input  [ DSP48E1_OPMODE_W -1:0] opmode;         //
    input  [DSP48E1_ALUMODE_W -1:0] alumode;        //
    input  [       WORD_EXT_W -1:0] casc_a_in;      //
    input  [           WORD_W -1:0] casc_b_in;      //
    output [       WORD_EXT_W -1:0] casc_a_out;     //
    output [           WORD_W -1:0] casc_b_out;     //
    
    //
    // A Port
    //
    wire [WORD_EXT_W -1:0] a_mux = AB_INPUT == "DIRECT" ? a : casc_a_in;
    reg  [WORD_EXT_W -1:0] a_reg1;
    reg  [WORD_EXT_W -1:0] a_reg2;

    assign casc_a_out = a_reg1;

    always @(posedge clk) begin
        if (ce_a1) a_reg1 <= a_mux;
        if (ce_a2) a_reg2 <= a_reg1;
    end
    
    //
    // B Port
    //
    wire [WORD_W -1:0] b_mux = AB_INPUT == "DIRECT" ? b : casc_b_in;
    reg  [WORD_W -1:0] b_reg1;
    reg  [WORD_W -1:0] b_reg2;

    assign casc_b_out = b_reg1;

    always @(posedge clk) begin
        if (ce_b1) b_reg1 <= b_mux;
        if (ce_b2) b_reg2 <= B_REG == 2 ? b_reg1 : b_mux;
    end

    //
    // OPMODE Port
    //
    reg [DSP48E1_OPMODE_W -1:0] opmode_reg;
    
    always @(posedge clk) begin
        if (ce_mode) opmode_reg <= opmode;
    end

    //
    // M, P
    //
    reg [MAC_W-1:0] m_reg;
    reg [MAC_W-1:0] p_reg;
    
    wire [MAC_W-1:0] a_pad = {{MAC_W-WORD_EXT_W{1'b0}}, a_reg2};
    wire [MAC_W-1:0] b_pad = {{MAC_W-WORD_W{1'b0}}, b_reg2};
    wire [MAC_W-1:0] p_pad = opmode_reg[5] ? p_reg : {MAC_W{1'b0}};
    
    assign p = p_reg;
    
    always @(posedge clk) begin
        if (ce_m) m_reg <= a_pad * b_pad;
        if (ce_p) p_reg <= m_reg + p_pad;
    end
    

    /*
    DSP48E1 #
    (
        .AREG                   (2),
        .BREG                   (B_REG),
        .CREG                   (0),
        .DREG                   (0),
        .ADREG                  (0),
        .MREG                   (1),
        .PREG                   (1),
        .ACASCREG               (1),
        .BCASCREG               (1),
        .INMODEREG              (0),
        .OPMODEREG              (1),
        .ALUMODEREG             (0),
        .CARRYINREG             (0),
        .CARRYINSELREG          (0),

        .A_INPUT                (AB_INPUT),
        .B_INPUT                (AB_INPUT),

        .USE_DPORT              ("FALSE"),
        .USE_MULT               ("DYNAMIC"),
        .USE_SIMD               ("ONE48"),

        .MASK                   ({DSP48E1_P_W{1'b1}}),
        .PATTERN                ({DSP48E1_P_W{1'b0}}),
        .SEL_MASK               ("MASK"),
        .SEL_PATTERN            ("PATTERN"),
        
        .USE_PATTERN_DETECT     ("NO_PATDET"),
        .AUTORESET_PATDET       ("NO_RESET")
    )
    DSP48E1_inst
    (
        .CLK                (clk),
    
        .CEA1               (ce_a1),
        .CEB1               (ce_b1),
        .CEA2               (ce_a2),
        .CEB2               (ce_b2),
        .CEAD               (1'b0),
        .CEC                (1'b0),
        .CED                (1'b0),
        .CEM                (ce_m),
        .CEP                (ce_p),
        .CEINMODE           (1'b0),
        .CECTRL             (ce_mode),
        .CEALUMODE          (1'b0),
        .CECARRYIN          (1'b0),

        .A                  ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, a}),
        .B                  ({{(DSP48E1_B_W-WORD_W){1'b0}}, b}),
        .C                  ({DSP48E1_C_W{1'b0}}),
        .D                  ({DSP48E1_D_W{1'b0}}),
        .P                  ({p_dummy, p}),
        
        .INMODE             (inmode),
        .OPMODE             (opmode),
        .ALUMODE            (alumode),

        .ACIN               ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, casc_a_in}),
        .BCIN               ({{(DSP48E1_B_W-WORD_W){1'b0}}, casc_b_in}),
        .ACOUT              ({casc_a_dummy, casc_a_out}),
        .BCOUT              ({casc_b_dummy, casc_b_out}),
        .PCIN               ({DSP48E1_P_W{1'b0}}),
        .PCOUT              (),
        .CARRYCASCIN        (1'b0),
        .CARRYCASCOUT       (),
 
        .RSTA               (1'b0),
        .RSTB               (1'b0),
        .RSTC               (1'b0),
        .RSTD               (1'b0),
        .RSTM               (1'b0),
        .RSTP               (1'b0),
        .RSTINMODE          (1'b0),
        .RSTCTRL            (1'b0),
        .RSTALUMODE         (1'b0),
        .RSTALLCARRYIN      (1'b0),

        .UNDERFLOW          (),
        .OVERFLOW           (),
        .PATTERNDETECT      (),
        .PATTERNBDETECT     (),

        .CARRYIN            (1'b0),
        .CARRYOUT           (),
        .CARRYINSEL         (3'b000),

        .MULTSIGNIN         (1'b0),
        .MULTSIGNOUT        ()
    );
    */
 

endmodule