path: root/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v

//======================================================================
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// Copyright (c) 2019, NORDUnet A/S All rights reserved.
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//======================================================================

module modexpng_dsp_slice_addsub_wrapper_xilinx
(
    clk,
    ce_abc,
    ce_p,
    ce_ctrl,
    ab, c, p,
    op_mode,
    alu_mode,
    carry_in_sel,
    casc_p_in,
    casc_p_out,
    carry_out
);

    `include "modexpng_dsp48e1.vh"
        
    input                              clk;
    input                              ce_abc;
    input                              ce_p;
    input                              ce_ctrl;
    input  [         DSP48E1_C_W -1:0] ab;
    input  [         DSP48E1_C_W -1:0] c;
    output [         DSP48E1_P_W -1:0] p;
    input  [    DSP48E1_OPMODE_W -1:0] op_mode;
    input  [   DSP48E1_ALUMODE_W -1:0] alu_mode;
    input  [DSP48E1_CARRYINSEL_W -1:0] carry_in_sel;
    input  [         DSP48E1_P_W -1:0] casc_p_in;
    output [         DSP48E1_P_W -1:0] casc_p_out;
    output                             carry_out;

    wire [       DSP48E1_A_W -1:0] a_int;
    wire [       DSP48E1_B_W -1:0] b_int;
    wire [       DSP48E1_C_W -1:0] c_int;
    wire [       DSP48E1_P_W -1:0] p_int;
    wire [DSP48E1_CARRYOUT_W -1:0] carry_out_int;

    assign {a_int, b_int} = {ab};
    assign {c_int}        = {c};
    assign {p}            = {p_int};
    assign {carry_out}    = {carry_out_int[DSP48E1_CARRYOUT_W-1]};

    DSP48E1 #
    (
        .AREG                   (1),
        .BREG                   (1),
        .CREG                   (1),
        .DREG                   (0),
        .ADREG                  (0),
        .MREG                   (0),
        .PREG                   (1),
        .ACASCREG               (1),
        .BCASCREG               (1),
        .INMODEREG              (0),
        .OPMODEREG              (1),
        .ALUMODEREG             (1),
        .CARRYINREG             (0),
        .CARRYINSELREG          (1),

        .A_INPUT                ("DIRECT"),
        .B_INPUT                ("DIRECT"),

        .USE_DPORT              ("FALSE"),
        .USE_MULT               ("NONE"),
        .USE_SIMD               ("ONE48"),

        .MASK                   ({DSP48E1_P_W{1'b1}}),
        .PATTERN                ({DSP48E1_P_W{1'b0}}),
        .SEL_MASK               ("MASK"),
        .SEL_PATTERN            ("PATTERN"),
        
        .USE_PATTERN_DETECT     ("NO_PATDET"),
        .AUTORESET_PATDET       ("NO_RESET")
    )
    DSP48E1_inst
    (
        .CLK                (clk),
    
        .CEA1               (1'b0),
        .CEB1               (1'b0),
        .CEA2               (ce_abc),
        .CEB2               (ce_abc),
        .CEAD               (1'b0),
        .CEC                (ce_abc),
        .CED                (1'b0),
        .CEM                (1'b0),
        .CEP                (ce_p),
        .CEINMODE           (1'b0),
        .CECTRL             (ce_ctrl),
        .CEALUMODE          (ce_ctrl),
        .CECARRYIN          (1'b0),

        .A                  (a_int),
        .B                  (b_int),
        .C                  (c_int),
        .D                  ({DSP48E1_D_W{1'b0}}),
        .P                  (p_int),
        
        .INMODE             ({DSP48E1_INMODE_W{1'b0}}),
        .OPMODE             (op_mode),
        .ALUMODE            (alu_mode),

        .ACIN               (),
        .BCIN               (),
        .ACOUT              (),
        .BCOUT              (),
        .PCIN               (casc_p_in),
        .PCOUT              (casc_p_out),
        .CARRYCASCIN        (1'b0),
        .CARRYCASCOUT       (),
 
        .RSTA               (1'b0),
        .RSTB               (1'b0),
        .RSTC               (1'b0),
        .RSTD               (1'b0),
        .RSTM               (1'b0),
        .RSTP               (1'b0),
        .RSTINMODE          (1'b0),
        .RSTCTRL            (1'b0),
        .RSTALUMODE         (1'b0),
        .RSTALLCARRYIN      (1'b0),

        .UNDERFLOW          (),
        .OVERFLOW           (),
        .PATTERNDETECT      (),
        .PATTERNBDETECT     (),

        .CARRYIN            (1'b0),
        .CARRYOUT           (carry_out_int),
        .CARRYINSEL         (carry_in_sel),

        .MULTSIGNIN         (1'b0),
        .MULTSIGNOUT        ()
    );

endmodule