| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-07-08 | Minor update, there's no need to update Aj inside of systolic loop. | Pavel V. Shatov (Meister) | |
| 2017-07-05 | Triple multiplier turns out to be an overkill in Verilog, started turning | Pavel V. Shatov (Meister) | |
| systolic multiplication into a separate procedure. | |||
 |
index : user/shatov/modexp_fpga_model | |
| Reference model was written to help debug Verilog code | git repositories |
| aboutsummaryrefslogtreecommitdiff |
path: root/modexp_fpga_systolic.cpp