user/shatov/modexp_fpga_model - Reference model was written to help debug Verilog code

Age	Commit message (Collapse)	Author
2017-08-12	Merge branch 'master' of git.cryptech.is:user/shatov/modexp_fpga_modelHEAD master	Pavel V. Shatov (Meister)

2017-08-11	Renamed some of the test vector components for improved consistency.	Pavel V. Shatov (Meister)

2017-08-11	Cosmetic changes.	Pavel V. Shatov (Meister)

2017-08-10	Generate additional quantities required for testing of CRT in hardware.	Pavel V. Shatov (Meister)

2017-08-06	Follow what Verilog does more closely.	Pavel V. Shatov (Meister)

2017-07-18	Changes to the model:	Pavel V. Shatov (Meister)
	* Follow what Verilog does more closely: FPGA can't do PP = P * P, because it can't read from two different block mem P locations at the same time, we have to do P1 = P2 = P, PP = P1 * P2 * Updated the test vector script to format additional quantities to help debug Verilog exponentiation module * Added the trick suggested by Bernd Paysan to help better conceal whether we're discarding multiplication result when the current exponent bit is not set
2017-07-08	Minor update, there's no need to update Aj inside of systolic loop.	Pavel V. Shatov (Meister)

2017-07-05	Turned systolic multiplication into a separate routine.	Pavel V. Shatov (Meister)

2017-07-05	Triple multiplier turns out to be an overkill in Verilog, started turning	Pavel V. Shatov (Meister)
	systolic multiplication into a separate procedure.
2017-06-29	Follow what Verilog does more precisely.	Pavel V. Shatov (Meister)

2017-06-24	Improved the model:	Pavel V. Shatov (Meister)
	* added CRT support * fixed bug in systolic array when operand width is not a multiple of array width
2017-06-13	Initial commit of faster modular exponentiation model based on systolic ↵	Pavel V. Shatov (Meister)
	architecture.