user/shatov/ecdsa_fpga_model - Reference model written to help debug Verilog code

Age	Commit message (Collapse)	Author
2021-04-12	* cleaned up a bit	Pavel V. Shatov (Meister)
	* removed redundant check and refined microcode * re-enabled previously forgotten test
2021-04-11	Updated microcode parser script.	Pavel V. Shatov (Meister)

2021-04-11	Updated the top layer to accomodate changes in the underlying architecture.	Pavel V. Shatov (Meister)

2021-04-11	Updated curve math layer to do multiplication using the Montgomery ladder	Pavel V. Shatov (Meister)
	method. Also added optional debugging output to help debug microcoded versions of double and add routines.
2021-04-11	Forgot to add copyright year	Pavel V. Shatov (Meister)

2021-04-11	* Microcode layer redesigned to take advantage of Montgomery ladder	Pavel V. Shatov (Meister)
	architecture. Instead of R and S there are now two working ("cycle") registers R0 and R1. After every cycle R0+R1 is placed in register S ("sum"), 2R0\|1 (depending on current multiplier bit) is placed in register T. Then the working variables are updated, final result ends up in R0. Due to the change of working registers, modular inversion routines were updated accordingly. * Added optional debugging output control
2021-04-11	Added debugging helper flag to dump outputs of modular operations.	Pavel V. Shatov (Meister)

2021-03-13	Fixed non-microcoded mode compile error	Pavel V. Shatov (Meister)

2018-12-19	* New hardware architecture	Pavel V. Shatov (Meister)
	* Randomized test vector
2017-02-06	Minor cleanup	Pavel V. Shatov (Meister)
	* Fixed misplaced comma in 'ecdsa_model.h' * Rewrote P-384 reduction routine to match the style used in P-256 reduction
2016-11-07	Forgot to mention one more paper in README.	Pavel V. Shatov (Meister)

2016-10-31	Initial commit of FPGA base point multiplier reference model for ECDSA ↵	Pavel V. Shatov (Meister)
	curves P-256 and P-384.