| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-04-11 | Forgot to add copyright year | Pavel V. Shatov (Meister) |
| 2021-04-11 | * Microcode layer redesigned to take advantage of Montgomery ladder | Pavel V. Shatov (Meister) |
| 2021-04-11 | Added debugging helper flag to dump outputs of modular operations. | Pavel V. Shatov (Meister) |
| 2021-03-13 | Fixed non-microcoded mode compile error | Pavel V. Shatov (Meister) |
| 2018-12-19 | * New hardware architecture | Pavel V. Shatov (Meister) |
| 2017-02-06 | Minor cleanup | Pavel V. Shatov (Meister) |
| 2016-11-07 | Forgot to mention one more paper in README. | Pavel V. Shatov (Meister) |
| 2016-10-31 | Initial commit of FPGA base point multiplier reference model for ECDSA curves... | Pavel V. Shatov (Meister) |
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index : user/shatov/ecdsa_fpga_model | |
| Reference model written to help debug Verilog code | git repositories |
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