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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2018-04-01 13:23:16 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2018-04-01 13:31:36 +0300
commit180949c2d91d9e82a896c8d9f46f3b7541506f52 (patch)
tree550158449373aaa537df217f85399ee493df5f79 /rtl
parent9fa6e368879d30835880b3bb0e87c8cf13dd9874 (diff)
Minor cleanup.HEADmaster
Diffstat (limited to 'rtl')
-rw-r--r--rtl/ecdsa256_wrapper.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/rtl/ecdsa256_wrapper.v b/rtl/ecdsa256_wrapper.v
index c6e93ea..0c19848 100644
--- a/rtl/ecdsa256_wrapper.v
+++ b/rtl/ecdsa256_wrapper.v
@@ -138,8 +138,8 @@ module ecdsa256_wrapper
//
case (addr_lsb)
//
- ADDR_CONTROL: reg_control <= write_data[1];
- ADDR_DUMMY: reg_dummy <= write_data[31:0];
+ ADDR_CONTROL: reg_control <= write_data[CONTROL_NEXT_BIT];
+ ADDR_DUMMY: reg_dummy <= write_data;
//
endcase
//
@@ -169,7 +169,7 @@ module ecdsa256_wrapper
// Register / Core Memory Selector
//
reg addr_msb_last;
- always @(posedge clk) addr_msb_last = addr_msb;
+ always @(posedge clk) addr_msb_last <= addr_msb;
assign read_data = (addr_msb_last == ADDR_MSB_REGS) ? tmp_read_data : read_data_core;