| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-04-17 | Additional test cases.HEADmaster | Pavel V. Shatov (Meister) | |
| 2018-04-06 | * Follow more closely what Verilog does | Pavel V. Shatov (Meister) | |
| * Don't use hardcoded numbers, use the ones built into fastecdsa package * Generate more test vectors to really abuse the core and trigger the rarely used code path in the point addition procedure | |||
| 2018-04-03 | Added missing symbols. | Pavel V. Shatov (Meister) | |
| 2018-04-03 | No line continuation needed in Verilog. | Pavel V. Shatov (Meister) | |
| 2018-04-03 | Verilog test vector generation. | Pavel V. Shatov (Meister) | |
| 2018-02-26 | Initial commit of C reference model for ECDH cores. | Pavel V. Shatov (Meister) | |
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index : user/shatov/ecdh_fpga_model | |
| Reference model written to help debug Verilog code | git repositories |
| aboutsummaryrefslogtreecommitdiff |
path: root/test_vectors