AgeCommit message (Expand)Author
2018-04-17Additional test cases.HEADmasterPavel V. Shatov (Meister)
2018-04-06 * Follow more closely what Verilog doesPavel V. Shatov (Meister)
2018-04-03Added missing symbols.Pavel V. Shatov (Meister)
2018-04-03No line continuation needed in Verilog.Pavel V. Shatov (Meister)
2018-04-03Verilog test vector generation.Pavel V. Shatov (Meister)
2018-04-01Don't override the curve if already selected.Pavel V. Shatov (Meister)
2018-02-26Fixed Makefile.Pavel V. Shatov (Meister)
2018-02-26Initial commit of C reference model for ECDH cores.Pavel V. Shatov (Meister)