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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-04-06 21:52:21 +0300 |
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| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-04-06 21:52:21 +0300 |
| commit | 5c26d791ba611a00af3a6010c014694f6582bf12 (patch) | |
| tree | b739a2f48441d800c5007f42e7d67e8d3ddc5671 /ecdh_fpga_model.cpp | |
| parent | 5e78217a13bcda8d06db5f4d8c7446bcef940cba (diff) | |
* Follow more closely what Verilog does
* Don't use hardcoded numbers, use the ones built into fastecdsa package
* Generate more test vectors to really abuse the core and trigger the rarely
used code path in the point addition procedure
Diffstat (limited to 'ecdh_fpga_model.cpp')
0 files changed, 0 insertions, 0 deletions